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SWITCHINGSPECIFICATIONS
1
T est
Level
AD6640AST
Parameter (Conditions)
T emp
Min
T yp
Max
Units
Maximum Conversion Rate
Minimum Conversion Rate
2
Aperture Delay (t
A
)
Aperture Uncertainty (Jitter)
ENCODE Pulsewidth High
3
ENCODE Pulsewidth Low
Output Delay (t
OD
) DV
CC
+3.3 V/5.0 V
4
Full
Full
+25
°
C
+25
°
C
+25
°
C
+25
°
C
Full
VI
IV
V
V
IV
IV
IV
65
MSPS
MSPS
ps
ps rms
ns
ns
ns
6.5
400
0.3
6.5
6.5
8.5
10.5
12.5
NOT ES
1
All switching specifications tested by driving ENCODE and
ENCODE
differentially.
2
A plot of Performance vs. Encode is shown in Figure 16 under T ypical Performance Characteristics.
3
A plot of Performance vs. Duty Cycle (Encode = 65 MSPS) is shown in Figure 17 under T ypical Performance Characteristics.
4
Outputs driving one LCX gate. Delay is measured from differential crossing of ENC,
ENC
to the time when all output data bits are within valid logic levels.
Specifications subject to change without notice.
AC SPECIFICATIONS
1
(AV
CC
= +5 V, DV
CC
= +3.3 V; ENCODE &
ENCODE
= 65 MSPS; T
MN
= –40
8
C, T
MAX
= +85
8
C)
T est
Level
AD6640AST
Parameter (Conditions)
T emp
Min
T yp
Max
Units
SNR
Analog Input
@ –1 dBFS
2.2 MHz
15.5 MHz
31.0 MHz
69.0 MHz
+25
°
C
+25
°
C
+25
°
C
+25
°
C
V
I
V
V
68
67.7
67.5
66
dB
dB
dB
dB
64
SINAD
Analog Input
@ –1 dBFS
2.2 MHz
15.5 MHz
31.0 MHz
69.0 MHz
+25
°
C
+25
°
C
+25
°
C
+25
°
C
V
I
V
V
68
67.2
67.0
65.5
dB
dB
dB
dB
63.5
Worst Harmonic
2
(2nd or 3rd)
Analog Input
@ –1 dBFS
2.2 MHz
15.5 MHz
31.0 MHz
69.0 MHz
+25
°
C
+25
°
C
+25
°
C
+25
°
C
V
I
V
V
80
80
79.5
78.5
dBc
dBc
dBc
dBc
74
Worst Harmonic
2
(4th or Higher)
Analog Input
@ –1 dBFS
2.2 MHz
15.5 MHz
31.0 MHz
69.0 MHz
+25
°
C
+25
°
C
+25
°
C
+25
°
C
V
I
V
V
85
85
85
84
dBc
dBc
dBc
dBc
74
Multitone SFDR (w/Dither)
3
Eight T ones @ –20 dBFS
T wo-T one IMD Rejection
4
F1, F2 @ –7 dBFS
Analog Input Bandwidth
5
Full
V
90
dBFS
Full
+25
°
C
V
80
dBc
V
300
MHz
NOT ES
1
All ac specifications tested by driving ENCODE and
ENCODE
differentially.
2
For a single test tone at –1 dBFS, the worst case spectral performance is typically limited by the direct or aliased 2nd or 3rd harmonic. If a system is designed such
that the 2nd and 3rd harmonics fall out-of-band, overall performance in the band of interest is typically improved by 5 dB. Worst Harmonic (4th or Higher) includes
4th and higher order harmonics and all other spurious components. Reference Figure 12 for more detail.
3
See Overcoming Static Nonlinearities with Dither section for details on improving SFDR performance. T o measure SFDR, eight tones from 14 MHz to 18 MHz
(0.5 MHz spacing) are swept from –20 dBFS to –90 dBFS. An open channel at 16 MHz is used to monitor SFDR.
4
F1 = 14.9 MHz, F2 = 16 MHz.
5
Specification is small signal bandwidth. Plots of Performance versus Analog Input Frequency are shown in Figures 10, 11 and 12. Sampling wide bandwidths
(5 MHz–15 MHz) should be limited to 70 MHz center frequency.
Specifications subject to change without notice.
REV. 0
–3–
AD6640
(AV
CC
= +5 V, DV
CC
= +3.3 V; ENCODE &
ENCODE
= 65 MSPS; T
MN
= –40
8
C, T
MAX
= +85
8
C)