參數(shù)資料
型號(hào)： AD6655BCPZ-1051
廠商： Analog Devices, Inc.
英文描述： IF Diversity Receiver
中文描述： IF分集接收機(jī)
文件頁(yè)數(shù)： 11/84頁(yè)
文件大?。?/td> 2012K
代理商： AD6655BCPZ-1051
AD6655
DIGITAL SPECIFICATIONS—AD6655BCPZ-125/AD6655BCPZ-150
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = 1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, unless otherwise noted.
Rev. 0 | Page 11 of 84
Table 6.
AD6655BCPZ-125
Typ
CMOS/LVDS/LVPECL
1.2
AVDD 0.3
1.1 V
1.2
0
10
10
4
8
10
AD6655BCPZ-150
Typ
CMOS/LVDS/LVPECL
1.2
AVDD 0.3
1.1 V
1.2
0
10
10
8
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
SYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
LOGIC INPUT (CSB)
1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK/DFS)
2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SDIO/DCS, SMI SDFS)
1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
Max
Min
Max
Unit
V
V p-p
V
V
V
V
μA
μA
pF
kΩ
V
V
V
V
μA
μA
pF
kΩ
V
V
μA
μA
kΩ
pF
V
V
μA
μA
kΩ
pF
V
V
μA
μA
kΩ
pF
0.2
6
AVDD + 1.6
AVDD
3.6
0.8
+10
+10
12
0.2
6
AVDD + 1.6
AVDD
3.6
0.8
+10
+10
12
4
10
CMOS
1.2
4
10
26
2
26
2
26
5
CMOS
1.2
4
10
26
2
26
2
26
5
AVDD 0.3
1.2
0
10
10
8
1.22
0
10
40
1.22
0
92
10
1.22
0
10
38
AVDD + 1.6
3.6
0.8
+10
+10
12
3.6
0.6
+10
132
3.6
0.6
135
+10
3.6
0.6
+10
128
AVDD 0.3
1.2
0
10
10
8
1.22
0
10
40
1.22
0
92
10
1.22
0
10
38
AVDD + 1.6
3.6
0.8
+10
+10
12
3.6
0.6
+10
132
3.6
0.6
135
+10
3.6
0.6
+10
128
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