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參數(shù)資料
| 型號(hào)： | AD6655BCPZ-1051 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | IF Diversity Receiver |
| 中文描述： | IF分集接收機(jī) |
| 文件頁數(shù)： | 43/84頁 |
| 文件大小： | 2012K |
| 代理商： | AD6655BCPZ-1051 |
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AD6655
Increment Gain (IG) and Decrement Gain (DG)
The increment gain and decrement gain indicators are intended
to be used together to provide information to enable external
gain control. The decrement gain indicator works in conjunction
with the coarse upper threshold bits, asserting when the input
magnitude is greater than the 3-bit value in the coarse upper
threshold register (Address 0x105). The increment gain indicator,
similarly, corresponds to the fine lower threshold bits except
that it is asserted only if the input magnitude is less than the
value programmed in the fine lower threshold register after the
dwell time elapses. The dwell time is set by the 16-bit dwell time
value located at Address 0x10A and Address 0x10B and is set in
units of ADC input clock cycles ranging from 1 to 65,535. The
fine lower threshold register is a 13-bit register that is compared
Rev. 0 | Page 43 of 84
with the magnitude at the output of the ADC. This comparison
is subject to the ADC clock latency but allows a finer, more
accurate comparison. The fine upper threshold magnitude is
defined by the following equation:
dBFS
= 20 log(
Threshold Magnitude
/2
13
)
The decrement gain output works from the ADC fast detect
output pins, providing a fast indication of potential overrange
conditions. The increment gain uses the comparison at the
output of the ADC, requiring the input magnitude to remain
below an accurate, programmable level for a predefined period
before signaling external circuitry to increase the gain.
The operation of the increment gain output and decrement gain
output is shown graphically in Figure 75.
UPPER THRESHOLD (COARSE OR FINE)
FINE LOWER THRESHOLD
IG
DG
F_LT
C_UT OR F_UT*
DWELL TIME
TIMER RESET BY
RISE ABOVE F_LT
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE F_LT
NOTE: OUTPUTS FOLLOW THE INSTANTEOUS SIGNAL LEVEL AND NOT THE ENVELOPE BUT ARE GUARANTEED ACTIVE FOR A MINIMUM OF 2 ADC CLOCK CYCLES.
Figure 75. Threshold Settings for C_UT, F_UT, F_LT, DG, and IG
*C_UT AND F_UT DIFFER ONLY IN ACCURACY AND LATENCY.
DWELL TIME
0
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