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參數(shù)資料
| 型號： | AD6655BCPZ-1501 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | IF Diversity Receiver |
| 中文描述： | IF分集接收機 |
| 文件頁數(shù)： | 38/84頁 |
| 文件大?。?/td> | 2012K |
| 代理商： | AD6655BCPZ-1501 |
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AD6655
NUMERICALLY CONTROLLED OSCILLATOR (NCO)
FREQUENCY TRANSLATION
This processing stage comprises a digital tuner consisting of
a 32-bit complex numerically controlled oscillator (NCO). The
two channels of the AD6655 share a single NCO. The NCO is
optional and can be bypassed by clearing Bit 0 of Register 0x11D.
This NCO block accepts a real input from the ADC stage and
outputs a frequency translated complex (I and Q) output.
The NCO frequency is programmed in Register 0x11E,
Register 0x11F, Register 0x120, and Register 0x121. These four
8-bit registers make up a 32-bit unsigned frequency programming
word. Frequencies between CLK/2 and +CLK/2 are represented
using the following frequency words:
0x8000 0000 represents a frequency given by CLK/2.
0x0000 0000 represents dc (frequency = 0 Hz).
0x7FFF FFFF represents CLK/2 CLK/2
32
.
Rev. 0 | Page 38 of 84
Use the following equation to calculate the NCO frequency:
Mod
NCO_FREQ
2
32
×
=
CLK
CLK
f
f
f
)
,
(
where:
NCO_FREQ
is a 32-bit twos complement number representing
the NCO frequency register.
f
is the desired carrier frequency in hertz (Hz).
f
CLK
is the AD6655 ADC clock rate in hertz (Hz).
NCO SYNCHRONIZATION
The AD6655 NCOs within a single part or across multiple parts
can be synchronized using the external SYNC input. Bit 3 and
Bit 4 of Register 0x100 allow the NCO to be resynchronized on
every SYNC signal or only on the first SYNC signal after the
register is written. A valid SYNC causes the NCO to restart at
the programmed phase offset value.
PHASE OFFSET
The NCO phase offset register at Address 0x122 and
Address 0x123 adds a programmable offset to the phase
accumulator of the NCO. This 16-bit register is interpreted as
a 16-bit unsigned integer. A 0x00 in this register corresponds
to no offset, and a 0xFFFF corresponds to an offset of 359.995°.
Each bit represents a phase change of 0.005°. This register allows
multiple NCOs to be synchronized to produce outputs with
predictable phase differences. Use the following equation to
calculate the NCO phase offset value:
NCO
_
PHASE
= 2
16
×
PHASE
/360
where:
NCO_PHASE
is a decimal number equal to the 16-bit binary
number to be programmed at Register 0x122 and Register 0x123.
PHASE
is the desired NCO phase in degrees.
NCO AMPLITUDE AND PHASE DITHER
The NCO block contains amplitude and phase dither to
improve the spurious performance. Amplitude dither improves
performance by randomizing the amplitude quantization errors
within the angular-to-Cartesian conversion of the NCO. This
option reduces spurs at the expense of a slightly raised noise
floor. With amplitude dither enabled, the NCO has an SNR of
>93 dB and an SFDR of >115 dB. With amplitude dither
disabled, the SNR is increased to >96 dB at the cost of SFDR
performance, which is reduced to 100 dB. The NCO amplitude
dither is recommended and is enabled by setting Bit 1 of
Register 0x11D.
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