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參數(shù)資料
| 型號： | AD6655BCPZ-1501 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | IF Diversity Receiver |
| 中文描述： | IF分集接收機(jī) |
| 文件頁數(shù)： | 53/84頁 |
| 文件大?。?/td> | 2012K |
| 代理商： | AD6655BCPZ-1501 |
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AD6655
Rev. 0 | Page 53 of 84
Addr.
(Hex)
0x104
Register
Name
Fast Detect
Control
(Local)
Coarse Upper
Threshold
(Local)
Fine Upper
Threshold
Register 0
(Local)
Fine Upper
Threshold
Register 1
(Local)
Fine Lower
Threshold
Register 0
(Local)
Fine Lower
Threshold
Register 1
(Local)
Increase Gain
Dwell Time
Register 0
(Local)
Increase Gain
Dwell Time
Register 1
(Local)
Signal
Monitor
DC
Correction
Control
(Global)
Signal
Monitor
DC Value
Channel A
Register 0
(Global)
Signal
Monitor
DC Value
Channel A
Register 1
(Global)
Signal
Monitor
DC Value
Channel B
Register 0
(Global)
Signal
Monitor
DC Value
Channel B
Register 1
(Global)
Signal
Monitor
SPORT
Control
(Global)
Bit 7
(MSB)
Open
Bit 6
Open
Bit 5
Open
Bit 4
Open
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Fast detect
enable
Default
Value
(Hex)
0x00
Default
Notes/
Comments
Fast Detect Mode Select[2:0]
0x105
Open
Open
Open
Open
Open
Coarse Upper Threshold[2:0]
0x00
0x106
Fine Upper Threshold[7:0]
0x00
0x107
Open
Open
Open
Fine Upper Threshold[12:8]
0x00
0x108
Fine Lower Threshold[7:0]
0x00
0x109
Open
Open
Open
Fine Lower Threshold[12:8]
0x00
0x10A
Increase Gain Dwell Time[7:0]
0x00
In ADC clock
cycles
0x10B
Increase Gain Dwell Time[15:8]
0x00
In ADC clock
cycles
0x10C
Open
DC
correction
freeze
DC Correction Bandwidth(k:[3:0])
DC
correction
for signal
path
enable
DC
correction
for signal
monitor
enable
0x00
0x10D
DC Value Channel A[7:0]
Read only
0x10E
Open
Open
DC Value Channel A[13:8]
Read only
0x10F
DC Value Channel B[7:0]
Read only
0x110
Open
Open
DC Value Channel B[13:8]
Read only
0x111
Open
RMS
magnitude
output
enable
Peak
detector
output
enable
Threshold
crossing
output
enable
SPORT SMI SCLK
divide
00 = Undefined
01 = divide by 2
10 = divide by 4
11 = divide by 8
SPORT
SMI SCLK
sleep
Signal
monitor
SPORT
output
enable
0x04
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