參數(shù)資料
型號(hào)： AD6655BCPZ-801
廠商： Analog Devices, Inc.
英文描述： IF Diversity Receiver
中文描述： IF分集接收機(jī)
文件頁(yè)數(shù)： 21/84頁(yè)
文件大?。?/td> 2012K
代理商： AD6655BCPZ-801
AD6655
Rev. 0 | Page 21 of 84
PIN 1
INDICATOR
1
D
1
D
1
D
2
D
2
D
2
D
2
D
2
D
2
D
2
D
2
D
2
D
2
D
3
D
3
D
3
D
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
4
D
D
D
F
F
F
F
D
F
F
F
F
S
C
C
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DRVDD
D1–
D1+
D2–
D2+
D3–
D3+
D4–
D4+
DCO–
DCO+
D5–
D5+
D6–
D6+
D7–
SCLK/DFS
SDIO/DCS
AVDD
AVDD
VIN+B
VIN–B
RBIAS
CML
SENSE
VREF
VIN–A
VIN+A
AVDD
SMI SDFS
SMI SCLK/PDWN
SMI SDO/OEB
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD6655
PARALLEL LVDS
TOP VIEW
(Not to Scale)
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
0
Figure 10. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)
Table 13. Pin Function Descriptions (Interleaved Parallel LVDS Mode)
Pin No.
Mnemonic
ADC Power Supplies
20, 64
DRGND
1, 21
DRVDD
24, 57
DVDD
36, 45, 46
AVDD
0
AGND
ADC Analog
37
VIN+A
38
VINA
44
VIN+B
43
VINB
39
VREF
40
SENSE
42
RBIAS
41
CML
49
CLK+
50
CLK
ADC Fast Detect Outputs
54
FD0+
53
FD0-
Type
Description
Ground
Supply
Supply
Supply
Ground
Digital Output Ground.
Digital Output Driver Supply (1.8 V to 3.3 V).
Digital Power Supply (1.8 V Nominal.)
Analog Power Supply (1.8 V Nominal.)
Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package.
Input
Input
Input
Input
Input/Output
Input
Input/Output
Output
Input
Input
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin () for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin () for Channel B.
Voltage Reference Input/Output.
Voltage Reference Mode Select. See Table 15 for details.
External Reference Bias Resistor.
Common-Mode Level Bias Output for Analog Inputs.
ADC Clock Input—True.
ADC Clock Input—Complement.
Output
Output
Channel A/Channel B LVDS Fast Detect Indicator 0—True. See Table 21 for details.
Channel A/Channel B LVDS Fast Detect Indicator 0—Complement. See Table 21 for
details.
Channel A/Channel B LVDS Fast Detect Indicator 1—True. See Table 21 for details.
Channel A/Channel B LVDS Fast Detect Indicator 1—Complement. See Table 21
for details.
Channel A/Channel B LVDS Fast Detect Indicator 2—True See Table 21 for details.
Channel A/Channel B LVDS Fast Detect Indicator 2—Complement. See Table 21 for
details.
Channel A/Channel B LVDS Fast Detect Indicator 3—True. See Table 21 for details.
Channel A/Channel B LVDS Fast Detect Indicator 3—Complement. See Table 21 for
details.
56
55
FD1+
FD1
Output
Output
59
58
FD2+
FD2
Output
Output
61
60
FD3+
FD3
Output
Output
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