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參數(shù)資料
| 型號(hào)： | AD6655BCPZ-801 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | IF Diversity Receiver |
| 中文描述： | IF分集接收機(jī) |
| 文件頁數(shù)： | 37/84頁 |
| 文件大小： | 2012K |
| 代理商： | AD6655BCPZ-801 |
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AD6655
DIGITAL DOWNCONVERTER
The AD6655 includes a digital processing section that provides
filtering and reduces the output data rate. This digital processing
section includes a numerically controlled oscillator (NCO),
a half-band decimating filter, an FIR filter, and a second coarse
NCO (f
ADC
/8 fixed value) for output frequency translation. Each
of these processing blocks (except the decimating half-band
filter) has control lines that allow it to be independently enabled
and disabled to provide the desired processing function. The
digital downconverter can be configured to output either real data
or complex output data. These blocks can be configured in five
recommended combinations to implement different signal
processing functions.
DOWNCONVERTER MODES
Table 18 details the recommended downconverter modes of
operation in the AD6655.
Rev. 0 | Page 37 of 84
Table 18. Downconverter Modes
Mode
NCO/Filter
1
Half-band filter only
2
Half-band filter and FIR filter
3
NCO and half-band filter
4
NCO, half-band filter, and FIR filter
5
NCO, half-band filter, FIR filter, and
f
ADC
/8 NCO
NUMERICALLY CONTROLLED OSCILLATOR (NCO)
Frequency translation is accomplished with an NCO. Each of
the two processing channels shares a common NCO. Amplitude
and phase dither can be enabled on chip to improve the noise and
spurious performance of the NCO. A phase offset word is available
to create a known phase relationship between multiple AD6655s.
Because the decimation filter prevents usage of half the Nyquist
spectrum, a means is needed to translate the sampled input
spectrum into the usable range of the decimation filter. To
achieve this, a 32-bit, fine tuning, complex NCO is provided.
This NCO/mixer allows the input spectrum to be tuned to dc,
where it can be effectively filtered by the subsequent filter
blocks to prevent aliasing.
HALF-BAND DECIMATING FILTER AND FIR FILTER
The goal of the AD6655 digital filter block is to allow the sample
rate to be reduced by a factor of 2 while rejecting aliases that fall
into the band of interest. The half-band filter is designed to operate
as either a low-pass or high-pass filter and to provide greater
than 100 dB of alias protection for 22% of the input rate of the
structure. For an ADC sample rate of 150 MSPS, this provides
Output Type
Real
Real
Complex
Complex
Real
a maximum usable bandwidth of 16.5 MHz when using the filter
in real mode (NCO bypassed) or a maximum usable bandwidth
of 33.0 MHz when using the filter in the complex mode (NCO
enabled).
The optional fixed-coefficient FIR filter provides additional
filtering capability to sharpen the half-band roll-off to enhance
the alias protection. It removes the negative frequency images
to avoid aliasing negative frequencies for real outputs.
f
ADC
/8 FIXED-FREQUENCY NCO
A fixed f
ADC
/8 NCO is provided to translate the filtered, decimated
signal from dc to f
ADC
/8 to allow a real output. Figure 68 to
Figure 71 show an example of a 20 MHz input as it is processed
by the blocks of the AD6655.
–50
–24
–14
14
24
50
–4
4
0
0
Figure 68. Example AD6655 Real 20 MHz Bandwidth Input Signal Centered at
14 MHz (f
ADC
= 100 MHz)
–50
–38
–28
0
10
50
–18 –10
0
Figure 69. Example AD6655 20 MHz Bandwidth Input Signal Tuned to DC
Using the NCO (NCO Frequency = 14 MHz)
–50
Figure 70. Example AD6655 20 MHz Bandwidth Input Signal wth the
Negative Image Filtered by the Half-Band and FIR Filters
–38
–28
0
10
50
–18 –10
0
–50
Figure 71. Example AD6655 20 MHz Bandwidth Input Signal Tuned to
f
ADC
/8 for Real Output
0.25
22.5
12.5
50
0
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