參數(shù)資料
型號: AD6655BCPZ-801
廠商: Analog Devices, Inc.
英文描述: IF Diversity Receiver
中文描述: IF分集接收機(jī)
文件頁數(shù): 47/84頁
文件大?。?/td> 2012K
代理商: AD6655BCPZ-801
AD6655
CHANNEL/CHIP SYNCHRONIZATION
The AD6655 has a SYNC input that allows the user flexible
synchronization options for synchronizing the internal blocks.
The sync feature is useful for guaranteeing synchronized operation
across multiple ADCs. The input clock divider, NCO, half-band
filters, and signal monitor block can be synchronized using the
SYNC input. Each of these blocks, except for the signal monitor,
can be enabled to synchronize on a single occurrence of the
SYNC signal or on every occurrence.
Rev. 0 | Page 47 of 84
The SYNC input is internally synchronized to the sample clock.
However, to ensure that there is no timing uncertainty between
multiple parts, the SYNC input signal should be synchronized
to the input clock signal. The SYNC input should be driven
using a single-ended CMOS type signal.
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