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參數(shù)資料
| 型號： | AD677KRZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 100KSPS 28-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | DSP，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 480mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，雙極 |
| 配用： | AD677-EB-ND - BOARD EVAL SAMPLING ADC AD677 |
AD677
REV. A
–4–
(TMIN to TMAX, VCC = +12 V
5%, VEE = –12 V
5%, VDD = +5 V
10%)
1
TIMING SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Units
Conversion Period
2, 3
tC
10
1000
s
CLK Period
4
tCLK
480
ns
Calibration Time
tCT
85532
tCLK
Sampling Time
tS
2
s
Last CLK to SAMPLE Delay
5
tLCS
2.1
s
SAMPLE Low
tSL
100
ns
SAMPLE to Busy Delay
tSS
75
ns
1st CLK Delay
tFCD
50
ns
CLK Low
6
tCL
50
ns
CLK High
6
tCH
50
ns
CLK to BUSY Delay
tCB
180
300
ns
CLK to SDATA Valid
tCD
50
100
175
ns
CLK to SCLK High
tCSH
100
180
300
ns
SCLK Low
tSCL
50
80
ns
SDATA to SCLK High
tDSH
50
80
ns
CAL High Time
tCALH
50
ns
CAL to BUSY Delay
tCALB
15
50
ns
NOTES
1See the “CONVERSION CONTROL” and “AUTOCALIBRATION” sections for detailed explanations of the above timing.
2Depends upon external clock frequency; includes acquisition time and conversion time. The maximum conversion period is specified to account for the droop of the
internal sample/hold function. Operation at slower rates may degrade performance.
3t
C = tFCD + 16
× t
CLK + tLCS.
4580 ns is recommended for optimal accuracy over temperature (not necessary during calibration cycle).
5If SAMPLE goes high before the 17th CLK pulse, the device will start sampling approximately 100 ns after the rising edge of the 17th CLK pulse.
6t
CH + tCL = tCLK and must be greater than 480 ns.
CAL
(INPUT)
BUSY
(OUTPUT)
CLK
*
(INPUT)
t
CT
t
CALH
t
CALB
t
CB
t
FCD
85530
85531
85532
1
23
t
CL
t
CH
t
CLK
*SHADED PORTIONS OF INPUT SIGNALS ARE OPTIONAL. FOR BEST PERFORMANCE, WE
RECOMMEND THAT THESE SIGNALS BE HELD LOW EXCEPT WHEN EXPLICITY SHOWN HIGH.
Figure 1. Calibration Timing
t
CB
BUSY
(OUTPUT)
t
FCD
t
CH
*SHADED PORTIONS OF INPUT SIGNALS ARE OPTIONAL. FOR BEST PERFORMANCE, WE
RECOMMEND THAT THESE SIGNALS BE HELD LOW EXCEPT WHEN EXPLICITY SHOWN HIGH.
SAMPLE*
(INPUT)
t
S
CLK
*
(INPUT)
1
23
15
16
17
t
S
t
LCS
MSB
BIT
2
BIT
15
BIT
13
BIT
14
BIT
16
SCLK
(OUTPUT)
SDATA
(OUTPUT)
OLD BIT 16
t
C
t
CD
t
SCL
t
DSH
t
SB
t
SL
t
CLK
t
CSH
t
CL
Figure 2. General Conversion Timing
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD677TD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROCIRCUIT, DIGITAL-LINEAR, FAST, SERIAL, 16-BIT, A/D CONVERTER, MULTICHIP SILICON |
| AD677TD/883B | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC 16-BIT Serial 100 kSPS SAMPLING RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體: |
| AD677TD883B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROCIRCUIT, DIGITAL-LINEAR, FAST, SERIAL, 16-BIT, A/D CONVERTER, MULTICHIP SILICON |
| AD678 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit 200 kSPS Complete Sampling ADC |
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