- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10031 > AD679AJ (Analog Devices Inc)IC ADC 14BIT SAMPLING 44-JLCC PDF資料下載
參數(shù)資料
| 型號： | AD679AJ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT SAMPLING 44-JLCC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 128k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 745mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-JLCC（16.39x16.39） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個單端，單極；1 個單端，雙極 |
AD679
REV. D
–12–
INTERFACING THE AD679 TO MICROPROCESSORS
The I/O capabilities of the AD679 allow direct interfacing to
general-purpose and DSP microprocessor buses. The asynchro-
nous conversion control feature allows complete flexibility and
control with minimal external hardware.
The following examples illustrate typical AD679 interface
configurations.
AD679 to TMS320C25
In Figure 9, the AD679 is mapped into the TMS320C25 I/O
space. AD679 conversions are initiated by issuing an OUT
instruction to Port 1. EOC status and the conversion result are
read in with an IN instruction to Port 1. A single wait state is
inserted by generating the processor READY input from
IS,
Port 1, and
MSC. Address line A0 provides HBE decoding to
select between the high and low bytes of data. This configura-
tion supports processor clock speeds of 20 MHz and is capable
of supporting processor clock speeds of 40 MHz if a NOP instruc-
tion follows each AD679 read instruction.
Figure 9. AD679 to TMS320C25 Interface
AD679 to 80186
Figure 10 shows the AD679 interfaced to the 80186 micropro-
cessor. This interface allows the 80186’s built-in DMA control-
ler to transfer the AD679 output into a RAM based FIFO buffer
of any length, with no microprocessor intervention.
In this application the AD679 is configured in the asynchronous
mode, which allows conversions to be initiated by an external
trigger source independent of the microprocessor clock. After
each conversion, the AD679 EOC signal generates a DMA
request to Channel 1 (DRQ1). The subsequent DMA READ
sequences the high and low byte AD679 data and resets the
interrupt latch. The system designer must assign a sufficient
priority to the DMA channel to ensure that the DMA request is
serviced before the next conversion is completed. This configu-
ration can be used with 6 MHz and 8 MHz 80186
processors.
Figure 10. AD679 to 80186 DMA Interface
AD679 to Analog Devices ADSP-2101
Figure 11 demonstrates the AD679 interfaced to an ADSP-2101.
With a clock frequency of 12.5 MHz, and instruction execution in
one 80 ns cycle, the digital signal processor supports the AD679
interface with one wait state.
The converter is configured to run asynchronously using a sam-
pling clock. The EOC output of the AD679 gets asserted at the
end of each conversion and causes an interrupt. Upon interrupt,
the ADSP-2101 immediately asserts its FO pin LOW. In the
following cycle, the processor starts a data memory read by pro-
viding an address on the DMA bus. The decoded address gener-
ates
OE for the converter, and the high byte of the conversion
result is read over the data bus. The read operation is extended
with one wait state and thus started and completed within two
processor cycles (160 ns). Next, the ADSP-2101 asserts its FO
HIGH. This allows the processor to start reading the lower byte
of data. This read operation executes in a similar manner to the
first and is completed during the next 160 ns.
Figure 11. AD679 to ADSP-2101 Interface
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-26M-MX-F3 | CONVERTER MOD DC/DC 10V 75W |
| MS3112E24-61P | CONN RCPT 61POS BOX MNT W/PINS |
| IDT72V3612L15PF8 | IC FIFO 64X36X2 15NS 120QFP |
| AD678BD | IC ADC 12BIT SAMPLING 28-CDIP |
| AD1555BPZRL | IC ADC PGA 24BIT LN 28-PLCC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD679AJZ | 制造商:Analog Devices 功能描述:ADC SGL FLASH 128KSPS 14BIT PARALLEL 44PIN JLCC - Rail/Tube |
| AD679BD | 功能描述:IC ADC 14BIT SAMPLING 28-CDIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個單端，單極 |
| AD679BJ | 功能描述:IC ADC 14BIT SAMPLING 44-JLCC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個單端，單極 |
| AD679JD | 功能描述:IC ADC 14BIT SAMPLING 28-CDIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個單端，單極 |
| AD679JN | 功能描述:IC ADC 14BIT 128KSPS 28-DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。