參數(shù)資料
型號(hào): AD1555BPZRL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 1/24頁(yè)
文件大?。?/td> 0K
描述: IC ADC PGA 24BIT LN 28-PLCC
標(biāo)準(zhǔn)包裝: 1
位數(shù): 24
采樣率(每秒): 256k
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 96mW
電壓電源: 雙 ±
工作溫度: -55°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC(11.51x11.51)
包裝: 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類(lèi)型: 1 個(gè)差分,雙極
其它名稱(chēng): AD1555BPZRLDKR
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
AD1555/AD1556
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
Analog Devices, Inc., 2002
FUNCTIONAL BLOCK DIAGRAM
MUX
PGA
REF DIVIDER
DAC
MODE CONTROL
LOGIC
OVERVOLTAGE
DETECTION
CLOCK
GENERATION
LOOP
FILTER
REFIN
REFCAP2
REFCAP1
AGND3
DGND
VL
–VA
+VA
AGND2
MODIN
PGAOUT
AGND1
CLKIN SYNC
BW0...BW2 RESET PWRDN GND
VL
AIN (+)
AIN (–)
TIN (+)
TIN (–)
AD1555
CB0...CB4
PGA
CONTROL
CONFIGURATION
REGISTER
STATUS
REGISTER
INPUT
MUX
MFLG
MDATA
TDATA
CSEL
MCLK
INPUT SHIFT
REGISTER
DIN
SCLK
CS
R/
W
DOUT
DRDY
RSEL
CLOCK DIVIDER
DATA
OUTPUT
MUX
DATA
REGISTER
AD1556
H/
S
ERROR
PGA0...PGA4
DIGITAL
FILTER
24-Bit - ADC
with Low Noise PGA
FEATURES
AD1555
Fourth Order
-
Modulator
Large Dynamic Range
116 dB Min, 120 dB Typical @ 1 ms
117 dB Typical @ 0.5 ms
Low Input Noise: 80 nV rms @ 4 ms with
Gain of 34,128
Low Distortion: –111 dB Max, –120 dB Typical
Low Intermodulation: 122 dB
Sampling Rate at 256 kSPS
Very High Jitter Tolerance
No External Antialias Filter Required
Programmable Gain Front End
Input Range:
2.25 V
Robust Inputs
Gain Settings: 1, 2.5, 8.5, 34, 128
Common-Mode Rejection (DC to 1 kHz)
93 dB Min, 101 dB Typical @ Gain of 1
77 mW Typical Low Power Dissipation
Standby Modes
AD1556
FIR Digital Filter/Decimator
Serial or Parallel Selection of Configuration
Output Word Rates: 250 SPS to 16 kSPS
6.2 mW Typ Low Power Dissipation
70
W in Standby Mode
Reference Design and Evaluation Board with
Software Available
APPLICATIONS
Seismic Data Acquisition Systems
Chromatography
Automatic Test Equipment
GENERAL DESCRIPTION
The AD1555 is a complete sigma-delta modulator, combined
with a programmable gain amplifier intended for low frequency,
high dynamic range measurement applications. The AD1555
outputs a ones-density bitstream proportional to the analog
input. When used in conjunction with the AD1556 digital filter/
decimator, a high performance ADC is realized.
The continuous-time analog modulator input architecture avoids
the need for an external antialias filter. The programmable gain
front end simplifies system design, extends the dynamic range,
and reduces the system board area. Low operating power and
standby modes makes the AD1555 ideal for remote battery-pow-
ered data acquisition systems.
The AD1555 is fabricated on Analog Devices’ BiCMOS process
that has high performance bipolar devices along with CMOS
transistors. The AD1555 and AD1556 are packaged, respectively,
in 28-lead PLCC and 44-lead MQFP packages and are specified
from –55
°C to +85°C (AD1556 and AD1555 B Grade) and from
0
°C to 85°C (AD1555 A Grade).
0
FREQUENCY – Hz
–120
–200
0
50
AMPLITUDE
dBr
100
150
200
250
300
–20
–100
–140
–180
–60
–80
–160
–40
350
400
450
500
fIN = 24.4Hz
SNR = 116.7dB
THD = –120.6dB
Figure 1. FFT Plot, Full-Scale AIN Input, Gain of 1
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