參數(shù)資料
型號(hào): IDT72V3612L15PF8
廠(chǎng)商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 1/24頁(yè)
文件大?。?/td> 0K
描述: IC FIFO 64X36X2 15NS 120QFP
標(biāo)準(zhǔn)包裝: 750
系列: 72V
功能: 異步
存儲(chǔ)容量: 4.6K(64 x 36 x2)
數(shù)據(jù)速率: 67MHz
訪(fǎng)問(wèn)時(shí)間: 15ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 120-LQFP
供應(yīng)商設(shè)備封裝: 120-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱(chēng): 72V3612L15PF8
1
3.3 VOLT CMOS SyncBiFIFOTM
64 x 36 x 2
IDT72V3612
1
JANUARY 2014
2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4659/5
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
FEATURES:
Two independent clocked FIFOs (64 x 36 storage capacity each)
buffering data in opposite directions
Supports clock frequencies up to 83 MHz
Fast access times of 8ns
Free-running CLKA and CLKB can be asynchronous or
coincident (simultaneous reading and writing of data on a
single clock edge is permitted)
Mailbox bypass Register for each FIFO
Programmable Almost-Full and Almost-Empty Flags
Microprocessor interface control logic
EFA , FFA , AEA , and AFA flags synchronized by CLKA
EFB , FFB , AEB , and AFB flags synchronized by CLKB
Passive parity checking on each port
Parity generation can be selected for each port
Available in space saving 120-pin thin quad flat package (TQFP)
Green parts available, see ordering information
DESCRIPTION:
TheIDT72V3612isdesignedtorunoffa3.3Vsupplyforexceptionallylow-
powerconsumption. Thisdeviceisamonolithichigh-speed,low-powerCMOS
bi-directionalclockedFIFOmemory. Itsupportsclockfrequenciesupto83MHz
andhasreadaccesstimesasfastas8ns. TheFIFOoperatesinIDTStandard
mode. Two independent 64 x 36 dual-port SRAM FIFOs on board the chip
bufferdatainoppositedirections. EachFIFOhasflagstoindicateemptyand
fullconditionsandtwoprogrammableflags(Almost-FullandAlmost-Empty)to
FUNCTIONAL BLOCK DIAGRAM
Mail 1
Register
Input
Register
Output
Register
CLKA
CSA
W/
RA
ENA
MBA
Port-A
Control
Logic
Device
Control
RST
CLKB
CSB
W/
RB
ENB
MBB
Port-B
Control
Logic
MBF1
4659 drw 01
Mail 2
Register
Write
Pointer
Read
Pointer
Status Flag
Logic
Parity
Gen/Check
A0 - A35
36
RAM
ARRAY
64 x 36
Parity
Generation
Parity
Gen/Check
Programmable Flag
Offset Register
Status Flag
Logic
Input
Register
Output
Register
RAM
ARRAY
64 x 36
Parity
Generation
Read
Pointer
PEFB
PGB
EFB
AEB
FFB
AFB
ODD/
EVEN
FFA
AFA
FS0
FS1
EFA
AEA
PGA
PEFA
MBF2
Write
Pointer
FIFO2
FIFO1
36
B0 - B36
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