參數(shù)資料
型號(hào): AD7147A-1ACBZ-RL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 46/69頁(yè)
文件大?。?/td> 0K
描述: IC CDC 13CH I2C W/RAM 25WLCSP
產(chǎn)品變化通告: 8mm Carrier Tape Changes 28/Feb/2012
標(biāo)準(zhǔn)包裝: 10,000
系列: CapTouch™
類(lèi)型: 電容數(shù)字轉(zhuǎn)換器
分辨率(位): 16 b
采樣率(每秒): 250k
數(shù)據(jù)接口: I²C,串行
電壓電源: 單電源
電源電壓: 2.6 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 25-UFBGA,WLCSP
供應(yīng)商設(shè)備封裝: 25-WLCSP
包裝: 帶卷 (TR)
AD7147A
Rev. B | Page 49 of 68
Table 31. STAGE_COMPLETE_INT_STATUS Register1
Address
Data Bit
Default
Value
Type
Name
Description
0x00A
[0]
0
R
STAGE0_COMPLETE_INT_STATUS
STAGE0 conversion-complete register interrupt status
1 = indicates STAGE0 conversion completed
[1]
0
R
STAGE1_COMPLETE_INT_STATUS
STAGE1 conversion-complete register interrupt status
1 = indicates STAGE1 conversion completed
[2]
0
R
STAGE2_COMPLETE_INT_STATUS
STAGE2 conversion-complete register interrupt status
1 = indicates STAGE2 conversion completed
[3]
0
R
STAGE3_COMPLETE_INT_STATUS
STAGE3 conversion-complete register interrupt status
1 = indicates STAGE3 conversion completed
[4]
0
R
STAGE4_COMPLETE_INT_STATUS
STAGE4 conversion-complete register interrupt status
1 = indicates STAGE4 conversion completed
[5]
0
R
STAGE5_COMPLETE_INT_STATUS
STAGE5 conversion-complete register interrupt status
1 = indicates STAGE5 conversion completed
[6]
0
R
STAGE6_COMPLETE_INT_STATUS
STAGE6 conversion-complete register interrupt status
1 = indicates STAGE6 conversion completed
[7]
0
R
STAGE7_COMPLETE_INT_STATUS
STAGE7 conversion-complete register interrupt status
1 = indicates STAGE7 conversion completed
[8]
0
R
STAGE8_COMPLETE_INT_STATUS
STAGE8 conversion-complete register interrupt status
1 = indicates STAGE8 conversion completed
[9]
0
R
STAGE9_COMPLETE_INT_STATUS
STAGE9 conversion-complete register interrupt status
1 = indicates STAGE9 conversion completed
[10]
0
R
STAGE10_COMPLETE_INT_STATUS
STAGE10 conversion-complete register interrupt status
1 = indicates STAGE10 conversion completed
[11]
0
R
STAGE11_COMPLETE_INT_STATUS
STAGE11 conversion-complete register interrupt status
1 = indicates STAGE11 conversion completed
[12]
0
R
GPIO_INT_STATUS
GPIO input pin status
1 = indicates level on GPIO pin has changed
[15:13]
Unused
Set to 0
1 Registers self-clear to 0 after readback if the limits are not exceeded.
Table 32. CDC 16-Bit Conversion Data Registers
Address
Data Bit
Default
Value
Type
Name
Description
0x00B
[15:0]
0
R
CDC_RESULT_S0
STAGE0 CDC 16-bit conversion data
0x00C
[15:0]
0
R
CDC_RESULT_S1
STAGE1 CDC 16-bit conversion data
0x00D
[15:0]
0
R
CDC_RESULT_S2
STAGE2 CDC 16-bit conversion data
0x00E
[15:0]
0
R
CDC_RESULT_S3
STAGE3 CDC 16-bit conversion data
0x00F
[15:0]
0
R
CDC_RESULT_S4
STAGE4 CDC 16-bit conversion data
0x010
[15:0]
0
R
CDC_RESULT_S5
STAGE5 CDC 16-bit conversion data
0x011
[15:0]
0
R
CDC_RESULT_S6
STAGE6 CDC 16-bit conversion data
0x012
[15:0]
0
R
CDC_RESULT_S7
STAGE7 CDC 16-bit conversion data
0x013
[15:0]
0
R
CDC_RESULT_S8
STAGE8 CDC 16-bit conversion data
0x014
[15:0]
0
R
CDC_RESULT_S9
STAGE9 CDC 16-bit conversion data
0x015
[15:0]
0
R
CDC_RESULT_S10
STAGE10 CDC 16-bit conversion data
0x016
[15:0]
0
R
CDC_RESULT_S11
STAGE11 CDC 16-bit conversion data
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