參數(shù)資料
型號(hào)： AD7147AACBZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 18/69頁(yè)
文件大?。?/td> 0K
描述： IC CDC 13CH SPI W/RAM 25WLCSP
產(chǎn)品變化通告： 8mm Carrier Tape Changes 28/Feb/2012
標(biāo)準(zhǔn)包裝： 10,000
系列： CapTouch™
類型： 電容數(shù)字轉(zhuǎn)換器
分辨率（位）： 16 b
采樣率（每秒）： 250k
數(shù)據(jù)接口： 串行，SPI?
電壓電源： 單電源
電源電壓： 2.6 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 25-UFBGA，WLCSP
供應(yīng)商設(shè)備封裝： 25-WLCSP
包裝： 帶卷 (TR)
AD7147A
Rev. B | Page 24 of 68
CAPACITANCE SENSOR BEHAVIOR WITH
CALIBRATION
The AD7147A on-chip adaptive calibration algorithm prevents
sensor detection errors such as the one shown in Figure 35.
This is achieved by monitoring the CDC ambient levels and
readjusting the initial STAGEx_OFFSET_HIGH and STAGEx_
OFFSET_LOW values according to the amount of ambient drift
measured on each sensor. Based on the new stage offset values,
the internal STAGEx_HIGH_THRESHOLD and STAGEx_
LOW_THRESHOLD values described in Equation 1 and
Equation 2 are automatically updated.
This closed-loop routine ensures the reliability and repeatable
operation of every sensor connected to the AD7147A when they
are subjected to dynamic environmental conditions. Figure 36
shows a simplified example of how the AD7147A applies the
adaptive calibration process, resulting in no interrupt errors
even with changing CDC ambient levels due to dynamic
environmental conditions.
CDC
O
U
T
P
UT
CO
DE
S
t
SENSOR 1 INT
ASSERTED
1
2
3
4
5
6
STAGEx_HIGH_THRESHOLD
(POSTCALIBRATED
REGISTER VALUE)
CHANGING ENVIRONMENTAL CONDITIONS
1INITIAL STAGEx_OFFSET_HIGH REGISTER VALUE.
2POSTCALIBRATED REGISTER STAGEx_HIGH_THRESHOLD.
3POSTCALIBRATED REGISTER STAGEx_HIGH_THRESHOLD.
4INITIAL STAGEx_LOW_THRESHOLD.
5POSTCALIBRATED REGISTER STAGEx_LOW_THRESHOLD.
6POSTCALIBRATED REGISTER STAGEx_LOW_THRESHOLD.
CDC AMBIENT
VALUE DRIFTING
STAGEx_LOW_THRESHOLD
(POSTCALIBRATED
REGISTER VALUE)
SENSOR 2 INT
ASSERTED
077
27-
036
Figure 36. Typical Sensor Behavior with Calibration Applied on the Data Path
SLOW FIFO
As shown in Figure 33, there are a number of FIFOs imple-
mented on the AD7147A. These FIFOs are located in Bank 3 of
the on-chip memory. The slow FIFOs are used by the on-chip
logic to monitor the ambient capacitance level from each sensor.
AVG_FP_SKIP and AVG_LP_SKIP
In Register 0x001, Bits[13:12] are the slow FIFO skip control for
full power mode, AVG_FP_SKIP. Bits[15:14] in the same register
are the slow FIFO skip control for low power mode, AVG_LP_
SKIP, and determine which CDC samples are not used (skipped)
in the slow FIFO. Changing the values of the AVG_FP_SKIP
and AVG_LP_SKIP bits slows down or speeds up the rate at
which the ambient capacitance value tracks the measured
capacitance value read by the converter.
Slow FIFO update rate in full power mode = AVG_FP_SKIP ×
[(3 × Decimation Rate) × (SEQUENCE_STAGE_NUM + 1) ×
(FF_SKIP_CNT + 1) × 4 × 106].
Slow FIFO update rate in low power mode =
((AVG_LP_SKIP + 1) × (3 × Decimation Rate) ×
(SEQUENCE_STAGE_NUM + 1) × (4 × 106))+
LP_CONV_DELAY.
The slow FIFO is used by the on-chip logic to track the ambient
capacitance value. The slow FIFO expects to receive samples from
the converter at a rate between 33 ms and 40 ms. AVG_FP_SKIP
and AVG_LP_SKIP are used to normalize the frequency of the
samples going into the FIFO, regardless of how many conversion
stages are in a sequence.
Determining the AVG_FP_SKIP and AVG_LP_SKIP values is
required only once during the initial setup of the capacitance
sensor interface. The recommended values for these settings
when using all 12 conversion stages on the AD7147A are as follows:
AVG_FP_SKIP = 00 = skip three samples
AVG_LP_SKIP = 00 = skip zero samples
SLOW_FILTER_UPDATE_LVL
SLOW_FILTER_UPDATE_LVL controls whether the most
recent CDC measurement goes into the slow FIFO (slow filter).
The slow filter is updated when the difference between the
current CDC value and the last value of the slow FIFO is
greater than the value of SLOW_FILTER_UPDATE_LVL,
which is in the Ambient Control 1 register (AMB_COMP_
CTRL1), Address 0x003.
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