參數(shù)資料
型號: AD7148ACPZ-1500RL7
廠商: Analog Devices Inc
文件頁數(shù): 24/57頁
文件大小: 0K
描述: IC CAP-TO-DGTL CONV PROG 16LFCSP
標(biāo)準(zhǔn)包裝: 1
類型: 電容性
觸摸面板接口: 2 線
輸入數(shù)/鍵: 8
分辨率(位): 16 b
數(shù)據(jù)接口: I²C,串行
數(shù)據(jù)速率/采樣率 (SPS,BPS): 250k
電壓基準(zhǔn): 內(nèi)部
電源電壓: 2.6 V ~ 3.3 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 16-LFCSP
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 781 (CN2011-ZH PDF)
其它名稱: AD7148ACPZ-1500RL7DKR
AD7148
Rev. A | Page 29 of 56
2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
3. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE X ARE DON'T CARE BITS.
4. 16-BIT REGISTER ADDRESS[A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE X ARE DON’T CARE BITS.
5. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
6. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
NOTES
1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
SDA
DEV
A6
DEV
A5
DEV
A4
R/W
A7
A6
SCLK
DEV
A3
A1
A0
1
26
23
4
17
18
19
20
25
DEV
A2
DEV
A1
DEV
A0
ACK
A15
A14
11
16
5
678
910
START
AD7148 DEVICE ADDRESS
A9
A8
REGISTER ADDRESS[A15:A8]
REGISTER ADDRESS[A7:A0]
ACK
D15
D14
D9
D8
35
27
28
29
34
37
36
43
38
44
D1
D0
D7
D6
REGISTER DATA[D15:D8]
REGISTER DATA[D7:D0]
ACK
45
46
ACK
STOP
DEV
A6
DEV
A5
DEV
A4
123
START
t8
t7
t6
t5
t4
t2
t1
t3
AD7148 DEVICE ADDRESS
07
15
5-
0
37
07155-
038
4. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE THE TWO LSB X's ARE DON'T CARE BITS.
5. 16-BIT REGISTER ADDRESS[A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE THE UPPER LSB X’s ARE DON’T CARE BITS.
6. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
7. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
8. THE R/W BIT IS SET TO A1 TO INDICATE A READBACK OPERATION.
Figure 38. Example of I2C Timing for Single Register Write Operation
NOTES
1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
3. THE MASTER GENERATES THE ACK AT THE END OF THE READBACK TO SIGNAL THAT IT DOES NOT WANT ADDITIONAL DATA.
SDA
DEV
A6
DEV
A5
DEV
A4
R/W
A7
A6
SCLK
DEV
A3
A1
A0
1
26
234
17
18
19
20
25
DEV
A2
DEV
A1
DEV
A0
ACK
A15
A14
11
16
5678
910
START
AD7148-1 DEVICE ADDRESS
A9
A8
REGISTER ADDRESS[A15:A8]
REGISTER ADDRESS[A7:A0]
ACK
35
28
30
34
37
36
44
38
45
D1
D0
D7
D6
REGISTER DATA[D7:D0]
SR
ACK
46
P
DEV
A6
DEV
A5
DEV
A4
1
23
t8
t7
t6
t
5
t4
t2
t1
t3
AD7148 DEVICE ADDRESS
ACK
27
AD7148-1 DEVICE ADDRESS
DEV
A6
DEV
A5
DEV
A1
DEV
A0
R/W
29
39
35
28
30
34
37
36
44
38
45
D1
D0
D7
D6
REGISTER DATA[D7:D0]
S
ACK
46
P
t
5
t4
AD7142-1 DEVICE ADDRESS
DEV
A6
DEV
A5
DEV
A1
DEV
A0
R/W
29
39
P
USING
REPEATED START
SEPARATE READ AND
WRITE TRANSACTIONS
ACK
Figure 39. Example of I2C Timing for Single Register Readback Operation
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