參數(shù)資料
型號: AD7148ACPZ-1500RL7
廠商: Analog Devices Inc
文件頁數(shù): 35/57頁
文件大?。?/td> 0K
描述: IC CAP-TO-DGTL CONV PROG 16LFCSP
標準包裝: 1
類型: 電容性
觸摸面板接口: 2 線
輸入數(shù)/鍵: 8
分辨率(位): 16 b
數(shù)據(jù)接口: I²C,串行
數(shù)據(jù)速率/采樣率 (SPS,BPS): 250k
電壓基準: 內(nèi)部
電源電壓: 2.6 V ~ 3.3 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 16-LFCSP
包裝: 標準包裝
產(chǎn)品目錄頁面: 781 (CN2011-ZH PDF)
其它名稱: AD7148ACPZ-1500RL7DKR
AD7148
Rev. A | Page 39 of 56
Table 23. STAGEx_HIGH_INT_EN Register
Address
Data Bit
Default
Value
Type
Mnemonic
Description
0x006
[0]
0
R/W
STAGE0_HIGH_INT_EN
STAGE0 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 high threshold is exceeded
[1]
0
R/W
STAGE1_HIGH_INT_EN
STAGE1 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE1 high threshold is exceeded
[2]
0
R/W
STAGE2_HIGH_INT_EN
STAGE2 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE2 high threshold is exceeded
[3]
0
R/W
STAGE3_HIGH_INT_EN
STAGE3 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE3 high threshold is exceeded
[4]
0
R/W
STAGE4_HIGH_INT_EN
STAGE4 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE4 high threshold is exceeded
[5]
0
R/W
STAGE5_HIGH_INT_EN
STAGE5 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE5 high threshold is exceeded
[6]
0
R/W
STAGE6_HIGH_INT_EN
STAGE6 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE6 high threshold is exceeded
[7]
0
R/W
STAGE7_HIGH_INT_EN
STAGE7 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE7 high threshold is exceeded
[15:8]
Unused
Set unused register bits to 0
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