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參數(shù)資料
| 型號： | AD7226KRZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 8BIT LC2MOS QUAD 20-SOIC |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 37 |
| 設置時間： | 4µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 4 |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 20-SOIC W |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 143k |
| 產(chǎn)品目錄頁面： | 784 (CN2011-ZH PDF) |
REV.
–6–
AD7226
INTERFACE LOGIC INFORMATION
Address lines A0 and A1 select which DAC will accept data
from the input port. Table I shows the selection table for the
four DACs with Figure 4 showing the input control logic. When
the
WR signal is LOW, the input latches of the selected DAC
are transparent and its output responds to activity on the data
bus. The data is latched into the addressed DAC latch on the
rising edge of
WR. While WR is high the analog outputs remain
at the value corresponding to the data held in their respective latches.
Table I. AD7226 Truth Table
AD7226 Control Inputs
AD7226
WR
A1
A0
Operation
HX
XNo Operation Device Not Selected
LL
L
DAC A Transparent
LL
DAC A Latched
LL
H
DAC B Transparent
LH
DAC B Latched
LH
L
DAC C Transparent
HL
DAC C Latched
LH
H
DAC D Transparent
HH
DAC D Latched
L = Low State, H = High State, X = Don’t Care
A0
A1
WR
TO LATCH A
TO LATCH B
TO LATCH C
TO LATCH D
Figure 4. Input Control Logic
t
DS
t
DH
t
AH
t
AS
VINL
VINH
VINL
VDD
DATA
ADDRESS
WR
0
t
WR
NOTES
1. ALL INPUT SIGNAL RISE AND FALL TIMES
MEASURED FROM 10% TO 90% OF VDD.
t
r = tf = 20ns OVER VDD RANGE.
2. TIMING MEASUREMENT REFERENCE LEVEL IS
3. SELECTED INPUT LATCH IS TRANSPARENT WHILE
WR IS
LOW, THUS INVALID DATA DURING THIS TIME CAN CAUSE
SPURIOUS OUTPUTS.
VINH + VINL
2
Figure 5. Write Cycle Timing Diagram
D
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD7226KRZ | 制造商:Analog Devices 功能描述:IC, DAC, 8BIT, 143KSPS, SOIC-20 |
| AD7226KRZ-REEL | 功能描述:IC DAC 8BIT QUAD W/AMP 20SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:- 產(chǎn)品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應商設備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD7226TD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Digital-to-Analog Converter |
| AD7226TE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Digital-to-Analog Converter |
| AD7226TE/883B | 制造商:Analog Devices 功能描述:DAC 4-CH R-2R 8BIT 20PIN LCC - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:CMOS DAC IC - Bulk |
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