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參數(shù)資料
| 型號(hào)： | AD7233ANZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT LC2MOS SRL 8-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 系列： | DACPORT® |
| 設(shè)置時(shí)間： | 10µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 168mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 8-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，雙極 |
| 采樣率（每秒）： | 300k |
REV. B
–2–
AD7233–SPECIFICATIONS1
(VDD = +12 V to +15 V,
2 V
SS = –12 V to –15 V,
2 GND = 0 V, R
L = 2 k
, CL = 100 pF
to GND. All specifications TMIN to TMAX unless otherwise noted.)
Parameter
A Version
B Version
Unit
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
12
Bits
Relative Accuracy
3
±1
±1/2
LSB max
Differential Nonlinearity
3
±0.9
LSB max
Guaranteed Monotonic
Bipolar Zero Error3
±6
LSB max
DAC Latch Contents 0000 0000 0000
Full-Scale Error
3
±8
LSB max
Full-Scale Temperature Coefficient
4
±30
ppm of FSR/
°C typ
Guaranteed By Process
DIGITAL INPUTS
Input High Voltage, VINH
2.4
V min
Input Low Voltage, VINL
0.8
V max
Input Current
IIN
±1
A max
VIN = 0 V to VDD
Input Capacitance
4
8
pF max
ANALOG OUTPUTS
Output Voltage Range
±5
±5V
DC Output Impedance
4
0.5
typ
AC CHARACTERISTICS
4
Voltage Output Settling Time
Settling Time to Within
±1/2 LSB of Final Value
Positive Full-Scale Change
10
s max
Typically 4
s; DAC Latch 100. . .000 to 011. . .111
Negative Full-Scale Change
10
s max
Typically 5
s; DAC Latch 011. . .111 to 100. . .000
Digital-to-Analog Glitch Impulse
3
30
nV secs typ
DAC Latch Contents Toggled Between All 0s and all 1s
Digital Feedthrough3
10
nV secs typ
LDAC = High
POWER REQUIREMENTS
VDD Range
10.8/16.5
V min/V max
For Specified Performance Unless Otherwise Stated
VSS Range
–10.8/–16.5
V min/V max
For Specified Performance Unless Otherwise Stated
IDD
10
mA max
Output Unloaded; Typically 7 mA at Thresholds
ISS
2
mA max
Output Unloaded; Typically 1 mA at Th
resholds
NOTES
1Temperature Ranges are as follows: A, B Versions: –40
°C to +85°C.
2Power Supply Tolerance: A, B Versions:
±10%.
3See Terminology.
4Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2
Limit at 25 C, TMIN, TMAX
Parameter
(All Versions)
Unit
Conditions/Comments
t1
3
200
ns min
SCLK Cycle Time
t2
15
ns min
SYNC to SCLK Falling Edge Setup Time
t3
70
ns min
SYNC to SCLK Hold Time
t4
0
ns min
Data Setup Time
t5
40
ns min
Data Hold Time
t6
0
ns min
SYNC High to LDAC Low
t7
20
ns min
LDAC Pulsewidth
t8
0
ns min
LDAC High to SYNC Low
NOTES
1Sample tested at 25
°C to ensure compliance. All input signals are specified with tr and tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figure 3.
3SCLK Mark/Space Ratio range is 40/60 to 60/40.
(VDD = +10.8 V to +16.5 V, VSS = –10.8 V to –16.5 V, GND = O V, RL = 2 k , CL = 100 pF. All
Specifications TMIN to TMAX unless otherwise noted.)
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