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參數(shù)資料
| 型號(hào)： | AD7233ANZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT LC2MOS SRL 8-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 系列： | DACPORT® |
| 設(shè)置時(shí)間： | 10µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 168mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 8-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，雙極 |
| 采樣率（每秒）： | 300k |
AD7233
REV. B
–5–
There are two ways in which the DAC latch and hence the ana-
log output may be updated. The status of the
LDAC input is
examined after
SYNC is taken low. Depending on its status, one
of two update modes is selected.
If
LDAC = 0 then the automatic update mode is selected. In
this mode the DAC latch and analog output are updated auto-
matically when the last bit in the serial data stream is clocked in.
The update thus takes place on the sixteenth falling SCLK edge.
If
LDAC = 1 then the automatic update is disabled and the
DAC latch is updated by taking
LDAC low any time after the
16-bit data transfer is complete. The update now occurs on the
falling edge of
LDAC. This facility is useful for simultaneous
update in multi-DAC systems. Note that the
LDAC input must
be taken back high again before the next data transfer is initiated.
SYNC
SCLK
SDIN
LDAC
RESET
16
COUNTER/
DECODER
GATING
SIGNAL
AUTO-UPDATE
CIRCUITRY
GATING
SCLK
DAC LATCH (12 BITS)
INPUT SHIFT REGISTER (16 BITS)
Figure 2. Simplified Loading Structure
DB15
DON’T CARE
DB14
DON’T CARE
DB13
DON’T CARE
DB12
DON’T CARE
DB11
MSB
DB1
DB0
LSB
t
2
t
1
t
4
t
5
t
3
t
6
t
7
t
8
SYNC
SCLK
SDIN
LDAC
Figure 3. Timing Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7233ANZ | 制造商:Analog Devices 功能描述:D/A Converter (D-A) IC |
| AD7233BN | 制造商:Analog Devices 功能描述:DAC 1-CH R-2R 12-bit 8-Pin PDIP Tube 制造商:Analog Devices 功能描述:SEMICONDUCTORSLINEAR |
| AD7233BNZ | 功能描述:IC DAC 12BIT SRL W/AMP 8PDIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:DACPORT® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁(yè)面:1398 (CN2011-ZH PDF) |
| AD7237 | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS DUAL 12-BIT DACPORT |
| AD7237A | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Dual 12-Bit DACPORTs |
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