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參數資料
| 型號： | AD7249 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual 12-Bit Serial DACPORT(雙通道LC2MOS 12位串行D/A轉換器) |
| 中文描述： | 雙路12位串行DACPORT（雙通道LC2MOS 12位串行的D / A轉換器） |
| 文件頁數： | 11/12頁 |
| 文件大小： | 232K |
| 代理商： | AD7249 |
AD7249
REV. 0
–11–
AD7249–68HC11 Interface
Figure 14 shows a serial interface between the AD7249 and the
68HC11 microcontroller. SCK of the 68HC11 drives SCLK of
the AD7249 while the MOSI output drives the serial data line
of the AD7249. T he
SYNC
signal is derived from a port line
(PC0 shown).
For correct operation of this interface, the 68HC11 should be
configured such that its CPOL bit is a 0 and its CPHA bit is a
1. When data is to be transmitted to the part, PC0 is taken low.
When the 68HC11 is configured like this, data on MOSI is
valid on the falling edge of SCK . T he 68HC11 transmits its se-
rial data in 8-bit bytes with only eight falling clock edges occur-
ring in the transmit cycle. T o load data to the AD7249, PC0 is
left low after the first eight bits are transferred and a second byte
of data is then transferred serially to the AD7249. When the
second serial transfer is complete, the PC0 line is taken high.
Figure 14 shows the
LDAC
input of the AD7249 being driven
from another bit programmable port line (PC1). As a result,
both DACs can be updated simultaneously by taking
LDAC
low after both DACs latches have updated.
SDIN
SCLK
SYNC
SDIN
LDAC
AD7249*
PC0
PC1
68HC11*
*ADDITIONAL PINS OMITTED FOR CLARITY.
MOSI
SDT
Figure 14. AD7249–68HC11 Interface
AD7249–87C51 Interface
A serial interface between the AD7249 and the 87C51 micro-
controller is shown in Figure 15. T X D of the 87C51 drives
SCLK of the AD7249 while RX D drives the serial data line of
the part. T he
SYNC
signal is derived from the port line P3.3
and the
LDAC
line is driven port line P3.2.
T he 87C51 provides the LSB of its SBUF register as the first
bit in the serial data stream. T herefore, the user will have to en-
sure that the data in the SBUF register is arranged correctly so
that the don’t care bits are the first to be transmitted to the
AD7249 and the last bit to be sent is the LSB of the word to be
loaded to the AD7249. When data is to be transmitted to the
part, P3.3 is taken low. Data on RX D is valid on the falling
edge of T X D. T he 87C51 transmits its serial data in 8-bit bytes
with only eight falling clock edges occurring in the transmit
cycle. T o load data to the AD7249, P3.3 is left low after the
first eight bits are transferred, and a second byte of data is then
transferred serially to the AD7249 with DB12 used to select the
appropriate DAC register. When the second serial transfer is
complete, the P3.3 line is taken high and then taken low again
to start the loading sequence to the second DAC (see timing
diagram Figure 8).
Figure 15 shows the
LDAC
input of the AD7249 driven from
the bit programmable port line P3.2. As a result, both DAC
outputs can be updated simultaneously by taking the
LDAC
line low following the completion of the write cycle to the sec-
ond DAC. Alternatively
LDAC
could be hardwired low and the
analog output will be updated on the sixteenth falling edge of
T X D after the
SYNC
signal for the DAC has gone low.
TDT
SDIN
SCLK
SYNC
SDIN
LDAC
AD7249*
P3.3
P3.2
87C51*
*ADDITIONAL PINS OMITTED FOR CLARITY.
RXD
Figure 15. AD7249–87C51 Interface
APPLICAT IONS
OPT O-ISOLAT E D INT E RFACE
In many process control type applications it is necessary to pro-
vide an isolation barrier between the controller and the unit
being controlled. Opto-isolators can provide voltage isolation
in excess of 3 k
. T he serial loading structure of the AD7249
makes it ideal for opto-isolated interfaces as the number of
interface lines is kept to a minimum.
Figure 16 shows a 2-channel isolated interface using the
AD7249.
T he sequence of events to program the output channels is as
follows.
1. T ake the
SYNC
line low.
2. T ransmit the 16-bit word for DAC A (DB 12 of the 16 bit
data word selects the DAC, DB12 = 0 to select DAC A) and
bring the
SYNC
line high after the 16 bits have been trans-
mitted.
3. Bring
SYNC
line low again and transmit 16 bits for DAC B,
bring
SYNC
back high at end of transmission.
4. Pulse the
LDAC
line low. T his updates both output chan-
nels simultaneously on the falling edge of
LDAC
.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7249AN | 功能描述:IC DAC 12BIT SRL W/REF 16-DIP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 數模轉換器 系列:DACPORT® 產品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設置時間:7µs 位數:16 數據接口:并聯 轉換器數目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應商設備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD7249ANZ | 功能描述:IC DAC 12BIT SRL W/REF 16-DIP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 數模轉換器 系列:DACPORT® 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設置時間:4µs 位數:12 數據接口:串行 轉換器數目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設備封裝:8-uMAX 包裝:管件 輸出數目和類型:2 電壓，單極 采樣率（每秒）:* 產品目錄頁面:1398 (CN2011-ZH PDF) |
| AD7249ANZ | 制造商:Analog Devices 功能描述:IC 12-BIT DAC |
| AD7249AR | 功能描述:IC DAC 12BIT SRL W/REF 16-SOIC RoHS:否 類別:集成電路 (IC) >> 數據采集 - 數模轉換器 系列:DACPORT® 產品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設置時間:7µs 位數:16 數據接口:并聯 轉換器數目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應商設備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD7249AR-REEL | 功能描述:數模轉換器- DAC LC2MOS DUAL 12-BIT SERIAL IC RoHS:否 制造商:Analog Devices 轉換器數量:4 DAC 輸出端數量:4 轉換速率: 分辨率:12 bit 接口類型:Serial (I2C) 穩(wěn)定時間: 最大工作溫度:+ 105 C 安裝風格: 封裝 / 箱體:TSSOP 封裝:Reel |
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