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參數(shù)資料
| 型號(hào)： | AD7249 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual 12-Bit Serial DACPORT(雙通道LC2MOS 12位串行D/A轉(zhuǎn)換器) |
| 中文描述： | 雙路12位串行DACPORT（雙通道LC2MOS 12位串行的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 232K |
| 代理商： | AD7249 |
AD7249
REV. 0
–9–
Bipolar (
6
5 V) Configuration
T he bipolar configuration for the AD7249, which gives an out-
put range of –5 V to +5 V, is achieved by connecting R
OFSA
,
R
OFSB
to V
REFIN
. T he AD7249 must be operated from dual sup-
plies to achieve this output voltage range. Either offset binary or
twos complement coding may be selected. Figure 10 shows the
connection diagram for bipolar operation. An AD586 provides
the reference voltage for the DAC but this could be provided by
the on-chip reference by connecting REFOUT to REFIN.
REFIN
DGND
AGND
12-BIT
DAC B
V
OUTB
R
OFSB
12-BIT
DAC A
V
OUTA
R
OFSA
V
SS
BIN/COMP
AD7249*
2R
2R
A1
2R
2R
A2
A2
V
DD
V
DD
–5 TO
+5V
–5 TO
+5V
V
SS
V
DD
AD586
V
OUT
+V
IN
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 10. Bipolar Configuration with External Reference
Bipolar Operation (T wos Complement Data Format)
T he AD7249 is configured for twos complement data format
by connecting
BIN
/COMP (Pin 7) high. T he analog output vs.
digital code is shown in T able II.
T able II. T wos Complement Bipolar Code T able
Input Data Word
MSB LSB
Analog Output, V
OUT
X X X Y 0111 1111 1111
X X X Y 0000 0000 0001
X X X Y 0000 0000 0000
X X X Y 1111 1111 1111
X X X Y 1000 0000 0001
X X X Y 1000 0000 0000
+REFIN
×
(2047/2048)
+REFIN
×
(1/2048)
0 V
–REFIN
×
(1/2048)
–REFIN
×
(2047/2048)
–REFIN
×
(2048/2048) = –REFIN
X = Don’t Care.
Y = DAC Select Bit, 0 = DAC A, 1 = DAC B.
Note: 1 LSB = REFIN/2048.
Bipolar Operation (Offset Binary Data Format)
T he AD7249 is configured for Offset Binary data format by con-
necting
BIN
/COMP (Pin 7) low. T he analog output vs. digital
code may be obtained by inverting the MSB in T able II.
APPLY ING T HE AD7249
Good printed circuit board layout is as important as the overall
circuit design itself in achieving high speed converter perfor-
mance. T he AD7249 works on an LSB size of 2.44 mV for the
unipolar 0 V to 10 V range and the bipolar
±
5 V range, when
using the unipolar 0 V to 5 V range the LSB size is 1.22 mV.
T herefore the designer must be conscious of minimizing noise in
both the converter itself and in the surrounding circuitry.
Switching mode power supplies are not recommended as switch-
ing spikes can feedthrough to the on-chip amplifier. Other causes of
concern are ground loops and feedthrough from microproces-
sors. T hese are factors which influence any high performance
converter, and proper printed circuit board layout which mini-
mizes these effects is essential to obtain high performance.
LAY OUT HINT S
Ensure that the layout has the digital and analog tracks sepa-
rated as much as possible. T ake care not to run any digital track
alongside an analog signal track. Establish a single point analog
ground separate from the logic system ground. Place this star
ground as close as possible to the AD7249. Connect all analog
grounds to this star point and also connect the AD7249 DGND
pin to this point. Do not connect any other digital grounds to
this analog ground point. Low impedance analog and digital
power supply common returns are essential for low noise opera-
tion of high performance converters. T o accomplish this track
widths should be kept a wide as possible and also the use of
ground planes minimizes impedance paths and also guards the
analog circuitry from digital noise.
NOISE
K eep the signal leads on the V
OUT A
and V
OUT B
signals and the
signal return leads to AGND as short as possible to minimize
noise coupling. In applications where this is not possible use a
shielded cable between the DAC outputs and their destination.
Reduce the ground circuit impedance as much as possible since
any potential difference in grounds between the DAC and its
destination device appears as an error voltage in series with the
DAC output.
Power Supply Decoupling
T o achieve optimum performance when using the AD7249, the
V
DD
and V
SS
lines should be decoupled to AGND using 0.1
μ
F
capacitors. In noisy environments it is recommended that 10
μ
F
capacitors be connected in parallel with the 0.1
μ
F capacitors.
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