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參數(shù)資料
| 型號(hào)： | AD7266BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 10/29頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 3CH 2MSPS 32-LFCSP |
| 設(shè)計(jì)資源： | AD7266 SAR ADC in DC-Coupled Differential and Single-Ended Appls (CN0039) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 2M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 33.6mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 12 個(gè)單端，單極；6 個(gè)差分，單極；6 個(gè)偽差分，單極 |
| 產(chǎn)品目錄頁(yè)面： | 777 (CN2011-ZH PDF) |
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AD7266
Rev. B | Page 17 of 28
The channels used for simultaneous conversions are selected via
the multiplexer address input pins, A0 to A2. The logic states of
these pins also need to be established prior to the acquisition
time; however, they may change during the conversion time
provided the mode is not changed. If the mode is changed from
fully differential to pseudo differential, for example, then the
acquisition time would start again from this point. The selected
input channels are decoded as shown in Table 6.
ANALOG INPUT SELECTION
The analog inputs of the AD7266 can be configured as single-
ended or true differential via the SGL/DIFF logic pin, as shown
in
. If this pin is tied to a logic low, the analog input
channels to each on-chip ADC are set up as three true
differential pairs. If this pin is at logic high, the analog input
channels to each on-chip ADC are set up as six single-ended
analog inputs. The required logic level on this pin needs to be
established prior to the acquisition time and remain unchanged
during the conversion time until the track-and-hold has returned
to track. The track-and-hold returns to track on the 13th rising
edge of SCLK after the
CS falling edge (see
). If the
level on this pin is changed, it will be recognized by the
AD7266; therefore, it is necessary to keep the same logic level
during acquisition and conversion to avoid corrupting the
conversion in progress.
The analog input range of the AD7266 can be selected as 0 V to
VREF or 0 V to 2 × VREF via the RANGE pin. This selection is
made in a similar fashion to that of the SGL/DIFF pin by setting
the logic state of the RANGE pin a time tacq prior to the falling
edge of CS. Subsequent to this, the logic level on this pin can be
altered after the third falling edge of SCLK. If this pin is tied to a
logic low, the analog input range selected is 0 V to VREF. If this
pin is tied to a logic high, the analog input range selected is 0 V
to 2 × VREF.
For example, in Figure 31 the SGL/DIFF pin is set at logic high
for the duration of both the acquisition and conversion times so
the analog inputs are configured as single ended for that
conversion (Sampling Point A). The logic level of the SGL/DIFF
changed to low after the track-and-hold returned to track and
prior to the required acquisition time for the next sampling
instant at Point B; therefore, the analog inputs are configured as
differential for that conversion.
OUTPUT CODING
The AD7266 output coding is set to either twos complement or
straight binary, depending on which analog input configuration
is selected for a conversion. Table 5 shows which output coding
scheme is used for each possible analog input configuration.
Table 5. AD7266 Output Coding
SGL/DIFF
Range
Output Coding
DIFF
SCLK
CS
114
14
1
A
SGL/DIFF
B
tACQ
04603-026
0 V to VREF
Twos complement
DIFF
0 V to 2 × VREF
Twos complement
SGL
0 V to VREF
Straight binary
SGL
0 V to 2 × VREF
Twos complement
PSEUDO DIFF
0 V to VREF
Straight binary
PSEUDO DIFF
Figure 31. Selecting Differential or Single-Ended Configuration
0 V to 2 × VREF
Twos complement
Table 6. Analog Input Type and Channel Selection
ADC A
ADC B
SGL/DIFF
A2
A1
A0
VIN+
VIN
VIN+
VIN
Comment
1
0
VA1
AGND
VB1
AGND
Single ended
1
0
1
VA2
AGND
VB2
AGND
Single ended
1
0
1
0
VA3
AGND
VB3
AGND
Single ended
1
0
1
VA4
AGND
VB4
AGND
Single ended
1
0
VA5
AGND
VB5
AGND
Single ended
1
0
1
VA6
AGND
VB6
AGND
Single ended
0
VA1
VA2
VB1
VB2
Fully differential
0
1
VA1
VA2
VB1
VB2
Pseudo differential
0
1
0
VA3
VA4
VB3
VB4
Fully differential
0
1
VA3
VA4
VB3
VB4
Pseudo differential
0
1
0
VA5
VA6
VB5
VB6
Fully differential
0
1
0
1
VA5
VA6
VB5
VB6
Pseudo differential
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