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參數(shù)資料
| 型號： | AD7266BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 3CH 2MSPS 32-LFCSP |
| 設(shè)計資源： | AD7266 SAR ADC in DC-Coupled Differential and Single-Ended Appls (CN0039) |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 2M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 33.6mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 12 個單端，單極；6 個差分，單極；6 個偽差分，單極 |
| 產(chǎn)品目錄頁面： | 777 (CN2011-ZH PDF) |
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AD7266
Rev. B | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04
60
3-
00
2
24
23
22
21
1
2
3
32
DV
DD
A0
CS
SC
L
K
D
OU
T
B
DG
ND
D
OU
T
A
V
DRI
V
E
20
19
18
17
VB2
VB1
AGND
DCAPB
RANGE
SGL/DIFF
A2
A1
9
10
11
12
13
V
B5
V
B4
V
B3
V
B6
V
A6
V
A5
V
A4
V
A3
14
15
16
4
5
6
7
8
VA2
VA1
AGND
DCAPA
AVDD
REF SELECT
DGND
31
30
29
28
27
26
25
AD7266
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
NOTES
1. THE EXPOSED METAL PADDLE ON THE BOTTOM OF THE LFCSP
PACKAGE SHOULD BE SOLDERED TO PCB GROUND.
Figure 2. Pin Configuration (CP-32-2)
04
60
3
-04
1
CS
SGL/DIFF
1
2
3
4
5
6
7
8
REF SELECT
AVDD
DCAPA
VA1
AGND
DGND
VA2
23
A2
22
21
RANGE
18
VB1
19
AGND
20
DCAPB
24
A1
17
VB2
PIN 1
9
V
A3
10
V
A4
11
V
A5
12
V
A6
13
V
B6
14
V
B5
15
V
B4
16
V
B3
32
DV
DD
31
V
DR
IV
E
30
D
OU
T
A
29
DG
ND
28
D
OU
T
B
27
SC
L
K
26 25
A0
AD7266
TOP VIEW
(Not to Scale)
Figure 3. Pin Configuration (SU-32-2)
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 29
DGND
Digital Ground. This is the ground reference point for all digital circuitry on the AD7266. Both DGND pins should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.
2
REF SELECT
Internal/External Reference Selection. Logic input. If this pin is tied to DGND, the on-chip 2.5 V reference is used as
the reference source for both ADC A and ADC B. In addition, Pin DCAPA and Pin DCAPB must be tied to decoupling
capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be supplied to the AD7266
through the DCAPA and/or DCAPB pins.
3
AVDD
Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7266. The
AVDD and DVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a
transient basis. This supply should be decoupled to AGND.
4, 20
DCAPA,
DCAPB
Decoupling Capacitor Pins. Decoupling capacitors (470 nF recommended) are connected to these pins to
decouple the reference buffer for each respective ADC. Provided the output is buffered, the on-chip reference can
be taken from these pins and applied externally to the rest of a system. The range of the external reference is
dependent on the analog input range selected.
5, 6, 19
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7266. All analog input signals and any
external reference signal should be referred to this AGND voltage. All three of these AGND pins should connect to
the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must not
be more than 0.3 V apart, even on a transient basis.
7 to 12
VA1 to VA6
Analog Inputs of ADC A. These may be programmed as six single-ended channels or three true differential analog
input channel pairs. See Table 6.
13 to 18
VB6 to VB1
Analog Inputs of ADC B. These may be programmed as six single-ended channels or three true differential analog
input channel pairs. See Table 6.
21
RANGE
Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the analog input
channels. If this pin is tied to a logic low, the analog input range is 0 V to VREF. If this pin is tied to a logic high when
CS goes low, the analog input range is 2 × VREF. See the
section for details.
22
SGL/DIFF
Logic Input. This pin selects whether the analog inputs are configured as differential pairs or single ended. A logic
low selects differential operation while a logic high selects single-ended operation. See the Analog Input
Selection section for details.
23 to 25
A2 to A0
Multiplexer Select. Logic inputs. These inputs are used to select the pair of channels to be simultaneously
converted, such as Channel 1 of both ADC A and ADC B, Channel 2 of both ADC A and ADC B, and so on. The pair
of channels selected may be two single-ended channels or two differential pairs. The logic states of these pins
need to be set up prior to the acquisition time and subsequent falling edge of CS to correctly set up the
multiplexer for that conversion. See the
section for further details and
for
multiplexer address decoding.
26
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7266
and framing the serial data transfer.
27
SCLK
Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7266. This clock
is also used as the clock source for the conversion process.
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