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參數(shù)資料
| 型號(hào)： | AD7266BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 3CH 2MSPS 32-LFCSP |
| 設(shè)計(jì)資源： | AD7266 SAR ADC in DC-Coupled Differential and Single-Ended Appls (CN0039) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 2M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 33.6mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 12 個(gè)單端，單極；6 個(gè)差分，單極；6 個(gè)偽差分，單極 |
| 產(chǎn)品目錄頁面： | 777 (CN2011-ZH PDF) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁
AD7266
Rev. B | Page 22 of 28
SERIAL INTERFACE
Figure 41 shows the detailed timing diagram for serial inter-
facing to the AD7266. The serial clock provides the conversion
clock and controls the transfer of information from the AD7266
during conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode,
at which point the analog input is sampled and the bus is taken
out of three-state. The conversion is also initiated at this point
and requires a minimum of 14 SCLKs to complete. Once 13
SCLK falling edges have elapsed, the track-and-hold goes back
into track on the next SCLK rising edge, as shown in
at Point B. If a 16 SCLK transfer is used, then two trailing zeros
appear after the final LSB. On the rising edge of
CS, the
conversion is terminated and DOUTA and DOUTB go back into
three-state. If CS is not brought high but is instead held low for a
further 14 (or 16) SCLK cycles on DOUTA, the data from
Conversion B is output on DOUTA (followed by two trailing zeros).
Likewise, if CS is held low for a further 14 (or 16) SCLK cycles
on DOUTB, the data from Conversion A is output on DOUTB. This
is illustrated in
where the case for DOUTA is shown. In
this case, the DOUT line in use goes back into three-state on the
32nd SCLK falling edge or the rising edge of
CS, whichever
occurs first.
A minimum of 14 serial clock cycles are required to perform
the conversion process and to access data from one conversion
on either data line of the AD7266. CS going low provides the
leading zero to be read in by the microcontroller or DSP. The
remaining data is then clocked out by subsequent SCLK falling
edges, beginning with a second leading zero. Thus, the first
falling clock edge on the serial clock has the leading zero
provided and also clocks out the second leading zero. The 12-bit
result then follows with the final bit in the data transfer valid on
the 14th falling edge, having being clocked out on the previous
(13th) falling edge. In applications with a slower SCLK, it may be
possible to read in data on each SCLK rising edge depending on
the SCLK frequency. The first rising edge of SCLK after the CS
falling edge would have the second leading zero provided, and
the 13th rising SCLK edge would have DB0 provided.
Note that with fast SCLK values, and thus short SCLK periods,
in order to allow adequately for t2, an SCLK rising edge may
occur before the first SCLK falling edge. This rising edge of
SCLK may be ignored for the purposes of the timing
descriptions in this section. If a falling edge of SCLK is coincident
with the falling edge of CS, then this falling edge of SCLK is not
acknowledged by the AD7266, and the next falling edge of
SCLK will be the first registered after the falling edge of CS.
CS
SCLK
1
5
13
DOUTA
DOUTB
2 LEADING ZEROS
THREE-
STATE
t4
2
34
t5
t3
tQUIET
t2
THREE-STATE
DB11
DB10
DB2
DB0
t6
t7
t8
0
DB1
B
DB9
DB8
t9
04603-034
Figure 41. Serial Interface Timing Diagram
CS
SCLK
1
5
15
DOUTA
THREE-
STATE
t4
2
34
16
t5
t3
t2
THREE-
STATE
t6
t7
14
ZERO
0
ZERO
DB11B
17
2 LEADING ZEROS
t10
32
DB11A
2 LEADING
ZEROS
DB10A
DB9A
ZERO
2 TRAILING ZEROS
ZERO
2 TRAILING ZEROS
04603-035
Figure 42. Reading Data from Both ADCs on One DOUT Line with 32 SCLKs
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