參數(shù)資料
型號(hào)： AD7276BRM
廠商： ANALOG DEVICES INC
元件分類(lèi)： ADC
英文描述： 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
中文描述： 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封裝： MO-187AA, MSOP-8
文件頁(yè)數(shù)： 15/20頁(yè)
文件大?。?/td> 255K
代理商： AD7276BRM
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15
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REV. PrF
PRELIMINARY TECHNICAL DATA
Preliminary Technical Data
AD7276/AD7277/AD7278
Table II provides some typical performance data with
various op-amps used as the input buffer under the same
set-up conditions.
Op-amp in the AD7276 SNR Performance
input buffer
TBD kHz Input
AD8510
TBD dB
AD8610
TBD dB
AD8038 TBD dB
AD8519
TBD dB
When no amplifier is used to drive the analog input, the
source impedance should be limited to low values. The
maximum source impedance will depend on the amount
of total harmonic distortion (THD) that can be
tolerated. The THD will increase as the source
impedance increases and performance will degrade. TPC
7 shows a graph of the Total Harmonic Distortion
versus Analog input frequency for different source
impedances when using a supply voltage of TBD V and
sampling at a rate of 3 MSPS.
Table II. AD7276 performance for various Input Buffers
Digital Inputs
The digital inputs applied to the AD7276/AD7277/
AD7278 are not limited by the maximum ratings which
limit the analog inputs. Instead, the digitals inputs applied
can go to TBDV and are not restricted by the V
DD
+ 0.3V
limit as on the analog inputs. For example, if the
AD7276/AD7277/AD7278 were operated with a V
DD
of
3V then 5V logic levels could be used on the digital
inputs. However, it is important to note that the data
output on SDATA will still have 3V logic levels when
V
DD
= 3V. Another advantage of SCLK and
restricted by the V
DD
+ 0.3V limit is the fact that power
supply sequencing issues are avoided. If
applied before V
DD
then there is no risk of latch-up as
there would be on the analog inputs if a signal greater
than 0.3V was applied prior to V
DD
.
not being
or SCLK are
MODES OF OPERATION
The mode of operation of the AD7276/AD7277/AD7278
is selected by controlling the logic state of the
during a conversion. There are two possible modes of
operation, Normal Mode and Power-Down Mode. The
point at which
is pulled high after the conversion has
been initiated will determine whether the AD7276/
AD7277/AD7278 will enter Power-Down Mode or not.
Similarly, if already in Power-Down then
whether the device will return to Normal operation or
remain in Power-Down. These modes of operation are
designed to provide flexible power management options.
These options can be chosen to optimize the power dissi-
pation/throughput rate ratio for different application
requirements.
Normal Mode
This mode is intended for fastest throughput rate perfor-
mance as the user does not have to worry about any
power-up times with the AD7276/AD7277/AD7278
remaining fully powered all the time. Figure 12 shows the
general diagram of the operation of the AD7276/AD7277/
AD7278 in this mode.
The conversion is iniated on the falling edge of
described in the Serial Interface section. To ensure the
part remains fully powered up at all times
low until at least 10 SCLK falling edges have elapsed after
the falling edge of
. If
is brought high any time
after the 10th SCLK falling, the part will remain powered
up but the conversion
will be terminated and SDATA will
go back into three-state.
For the AD7276 a minimum of 14 serial clock cycles are
required to complete the conversion and access the
complete conversion result. For the AD7277 and AD7278
a minimum of 12 and 10 serial clock cycles are required
to complete the conversion and access the complete con-
version result, respectively.
may idle high until the next conversion or may idle
low until
returns high sometime prior to the next
conversion (effectively idling
Once a data transfer is complete (SDATA has returned to
three-state), another conversion can be initiated after the
quiet time, t
QUIET
, has elapsed by bringing
signal
can control
as
must remain
low).
low again.
Figure 12. Normal Mode Operation
12
14
16
AD7276/77/78
VALIDDATA
SDATA
SCLK
&6
1
10
相關(guān)PDF資料
PDF描述
AD7276BUJ-REEL 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
AD7277 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
AD7277BRM 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
AD7277BUJ-REEL 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
AD7278 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
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