參數(shù)資料
型號: AD7276BRM
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
中文描述: 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封裝: MO-187AA, MSOP-8
文件頁數(shù): 19/20頁
文件大?。?/td> 255K
代理商: AD7276BRM
19
REV. PrF
PRELIMINARY TECHNICAL DATA
Preliminary Technical Data
AD7276/AD7277/AD7278
Figure 18. AD7278 Serial Interface Timing Diagram
&6
11
15
t
5
16
t
quiet
THREE-STATE
t
8
14
ZERO
ZERO
6TRAILING ZERO
S
ZERO
B
SCLK
1
SDATA
2 LEADING
ZERO
S
THREE-
STATE
t
4
2
3
4
t
3
t
convert
t
2
DB6
t
6
t
7
ZERO
Z
t
1
1/ THROUGHPUT
DB7
DB0
DB1
8
9
10
Figure 17. AD7277 Serial Interface Timing Diagram
&6
13
15
t
5
16
t
quiet
THREE-STATE
t
8
14
ZERO
ZERO
4TRAILING ZERO
S
ZERO
ZERO
B
SCLK
1
SDATA
2 LEADING
ZERO
S
THREE-
STATE
t
4
2
3
4
t
3
t
convert
t
2
DB8
t
6
t
7
ZERO
Z
t
1
1/ THROUGHPUT
DB9
DB0
DB1
10
11
12
AD7278 in a 10 SCLK’s cycle Serial Interface
For the AD7278, if
edge after the 2 leading zeros and the 8 bits of the
conversion have been provided, the part can achieve a
4.2MSPS throughput rate. For the AD7278, the track and
hold goes back into track in the 9th rising edge. In that
case, a f
SCLK
= 52 MHz and a throughput of 4.2MSPS,
gives a cycle time of t
2
+ 8.5(1/f
SCLK
) + t
ACQ
= 238ns.
With t
2
= TBDns min, this leaves t
ACQ
to be TBDns.
This TBDns satisfies the requirement of 50 ns for t
ACQ
.
is brought high in the 10th rising
From Figure 19, t
ACQ
comprises of 0.5(1/f
SCLK
) + t
8
+
t
QUIET
, where t
8
= TBDns max. This allows a value of
TBDns for t
QUIET
satisfying the minimum requirement of
TBDns.
Figure 19. AD7278 in a 10 SCLK Cycle Serial Interface
&6
SCLK
t
1
1
5
9
SDATA
2 LEADING ZERO
S
3-STATE
3-STATE
DB7
DB6
DB0
ZERO
Z
DB1
2
3
4
t
QUIET
t
convert
t
2
t
6
t
8
10
B
1/ THROUGHPUT
t
ACQ
DB5
8.5(1/fSCLK)
相關PDF資料
PDF描述
AD7276BUJ-REEL 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
AD7277 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
AD7277BRM 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
AD7277BUJ-REEL 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
AD7278 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
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