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參數(shù)資料
| 型號： | AD7303BN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84% |
| 中文描述： | SERIAL INPUT LOADING, 1.2 us SETTLING TIME, 8-BIT DAC, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 361K |
| 代理商： | AD7303BN |
AD7303
–10–
REV. 0
Bit Location
Mnemonic
Description
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7–DB0
/EXT
X
LDAC
PDB
PDA
A
/B
CR1
CR0
Data
Selects between internal and external reference.
Uncommitted bit.
Load DAC bit for synchronous update of DAC outputs.
Power-down DAC B.
Power-down DAC A.
Address bit to select either DAC A or DAC B.
Control Bit 1 used in conjunction with CR0 to implement the various data loading functions.
Control Bit 0 used in conjunction with CR1 to implement the various data loading functions.
These bits contain the data used to update the output of the DACs. DB7 is the MSB and
DB0 the LSB of the 8-bit data word.
CONTROL BITS
LDAC
A
/B
CR1
CR0
Function Implemented
0
0
0
0
0
0
0
1
X
0
1
0
1
0
1
0
0
0
0
1
1
1
1
X
0
1
1
0
0
1
1
X
Both DAC registers loaded from shift register.
Update DAC A input register from shift register.
Update DAC B input register from shift register.
Update DAC A DAC register from input register.
Update DAC B DAC register from input register.
Update DAC A DAC register from shift register.
Update DAC B DAC register from shift register.
Load DAC A input register from shift register and update
both DAC A and DAC B DAC registers.
Load DAC B input register from shift register and update
both DAC A and DAC B DAC registers outputs.
1
1
X
X
INT
/EXT
Function
0
1
Internal V
DD
/2 reference selected.
External reference selected; this external reference is applied at the REF pin and ranges from
1 V to V
DD
/2.
PDA
PDB
Function
0
0
1
1
0
1
0
1
Both DACs active.
DAC A active and DAC B in power-down mode.
DAC A in power-down mode and DAC B active.
Both DACs powered down.
DB15 (MSB)
INT
/EXT
|––––––––––––––––––––––––– Control Bits –––––––––––––––––––––––––|––––––––––––––––––––––––– Data Bits –––––––––––––––––––––––––|
DB0 (LSB)
DB1
X
LDAC
PDB
PBA
A
/B
CR1
CR0
DB7
DB6
DB5
DB4
DB3
DB2
DB0
Figure 24. Input Shift Register Contents
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| AD7304 | ECONOLINE: REC2.2-S_DR/H1 - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- UL94V-0 Package Material- Continuous Short Circiut Protection- Internal SMD design- 100% Burned In- Efficiency to 75% |
| AD7304BN | ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84% |
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