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參數(shù)資料
| 型號(hào)： | AD7303BN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84% |
| 中文描述： | SERIAL INPUT LOADING, 1.2 us SETTLING TIME, 8-BIT DAC, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 361K |
| 代理商： | AD7303BN |
AD7303
–3–
REV. 0
TIMING CHARACTERISTICS
1, 2
Parameter
Limit at T
MIN
, T
MAX
(B Version)
Units
Conditions/Comments
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
33
13
13
5
5
4.5
4.5
33
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Time
SCLK High Time
SCLK
Low Time
SYNC
Setup Time
Data Setup Time
Data Hold Time
SYNC
Hold Time
Minimum
SYNC
High Time
NOTES
1
Sample tested at +25
°
C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2,
tr and tf should not exceed 1
μ
s on any input.
2
See Figures 1 and 2.
SCLK (I)
SYNC
(I)
DIN (I)
DB15
DB0
t
5
t
6
t
2
t
3
t
4
t
7
t
4
t
8
t
1
Figure 1. Timing Diagram for Continuous 16-Bit Write
SCLK (I)
SYNC
(I)
DIN (I)
DB15
DB8
t
5
t
6
t
2
t
3
t
4
t
7
DB7
DB0
t
5
t
6
t
8
t
1
Figure 2. Timing Diagram for 2
×
8-Bit Writes
(V
DD
= +2.7 V to +5.5 V; GND = 0 V; Reference = Internal V
DD
/2 Reference; all specifications
T
MIN
to T
MAX
unless otherwise noted)
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| AD7304 | ECONOLINE: REC2.2-S_DR/H1 - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- UL94V-0 Package Material- Continuous Short Circiut Protection- Internal SMD design- 100% Burned In- Efficiency to 75% |
| AD7304BN | ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84% |
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