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參數(shù)資料
| 型號(hào)： | AD7303BN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84% |
| 中文描述： | SERIAL INPUT LOADING, 1.2 us SETTLING TIME, 8-BIT DAC, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 361K |
| 代理商： | AD7303BN |
AD7303
–14–
REV. 0
AD7303 to 68HC11 Interface Program Source Code
*
PORTC
*
DDRC
PORTD
*
DDRD
SPCR
*
SPSR
*
SPDR
*
* SDI RAM Variables:
EQU
$1003
Port C Control Register
"SYNC, 0, 0, 0, 0, 0, 0, 0"
Port C Data Direction
Port D Data Register
"0, 0, 0, SCLK, DIN, 0, 0, 0"
Port D Data Direction
SPI Control Register
"SPIE, SPE, DWOM, MSTR, CPOL, CPHA, SPR1, SPR0"
SPI Status Register
"SPIF, WCOL, 0, MODF, 0, 0, 0, 0"
SPI Data Register, Read Buffer, Write Shifter
EQU
EQU
$1007
$1008
EQU
EQU
$1009
$1028
EQU
$1029
EQU
$102A
DIN 1 is eight MSBs, Control BYTE
DIN 2 is eight LSBs, Data BYTE
DAC requires 2*8-bit Writes
DIN BYTE 1: "
INT
/EXT, X, LDAC, PDB, PBA,
A
/B, CR1, CR0"
DIN BYTE 2: " DB7, DB6, DB5, DB4, DB3, DB2, DB1, DB0"
DIN1
DIN2
*
EQU
EQU
$00
$01
ORG
LDS
$C000
#$CFFF
Start of users ram
Top of C page Ram
INIT
*
LDAA
#$80
1, 0, 0, 0, 0, 0, 0, 0
SYNC is High
Initialize Port C Outputs
1, 0, 0, 0, 0, 0, 0, 0
SYNC enabled as output
*
STAA
LDAA
STAA
PORTC
#$80
DDRC
*
LDAA
#$00
0, 0, 0, 0, 0, 0, 0, 0
SCLK is low, DIN is low
Initialize Port D outputs
*
STAA
PORTD
Power Supply Bypassing and Grounding
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD7303 is mounted should be designed so that the analog and
digital sections are separated, and confined to certain areas of
the board. If the AD7303 is in a system where multiple
devices require an AGND to DGND connection, the connec-
tion should be made at one point only. The star ground point
should be established as closely as possible to the AD7303. The
AD7303 should have ample supply bypassing of 10
μ
F in paral-
lel with 0.1
μ
F on the supply located as closely to the package as
possible, ideally right up against the device. The 10
μ
F capaci-
tors are the tantalum bead type. The 0.1
μ
F capacitor should
have low Effective Series Resistance (ESR) and Effective Series
Inductance (ESI), like the common ceramic types that provide a
low impedance path to ground at high frequencies to handle
transient currents due to internal logic switching.
The power supply lines of the AD7303 should use as large a
trace as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching sig-
nals such as clocks should be shielded with digital ground to
avoid radiating noise to other parts of the board, and should
never be run near the reference inputs. Avoid crossover of digi-
tal and analog signals. Traces on opposite sides of the board
should run at right angles to each other. This reduces the effects of
feedthrough through the board. A microstrip technique is by far
the best, but not always possible with a double-sided board. In
this technique, the component side of the board is dedicated to
ground plane while signal traces are placed on the solder side.
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| AD7304BN | ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84% |
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