參數(shù)資料
型號(hào): AD7305BR
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: +3 V/+5 V, Rail-to-Rail Quad, 8-Bit DAC
中文描述: PARALLEL, 8 BITS INPUT LOADING, 1 us SETTLING TIME, 8-BIT DAC, PDSO20
封裝: MS-013AC, SOIC-20
文件頁(yè)數(shù): 4/14頁(yè)
文件大?。?/td> 936K
代理商: AD7305BR
AD7304/AD7305
4
REV. A
SDI
CLK
CS
LDAC
SA
SI
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
t
CSH
t
LD2
t
CSS
t
LD1
SDI
CLK
CLR
LDAC
FS
ZS
V
OUT
t
DS
t
DH
t
CL
t
CH
t
LDW
t
S
t
CLRW
t
S
1 LSB
ERROR BAND
Figure 2. AD7304 Timing Diagram
t
SDR
SDI/SHDN
I
DD
t
SDN
Figure 3. AD7304 Timing Diagram
Table I. AD7304 Control Logic Truth Table
CS
CLK
LDAC CLR
Serial Shift Register Function
Input REG Function
DAC Register Function
H
L
+
H
H
H
X
+
L
X
X
X
H
H
H
L
H
H
H
H
H
H
+
No Effect
Data Advanced 1 Bit
No Effect
No Effect
No Effect
No Effect
No Effect
No Effect
Updated with SR Contents
2
Latched with SR Contents
2
Loaded with 00
H
Latched with 00
H
No Effect
No Effect
No Effect
All Input Register Contents Transferred
3
Loaded with 00
H
Latched with 00
H
NOTES
1
+ positive logic transition;
– negative logic transition; X Don’t Care.
2
One Input Register receives the data bits D7–D0 decoded from the SR address bits (A1, A0); where REG A = (0, 0); B = (0, 1); C = (1, 0); D = (1, 1).
3
LDAC
is a level-sensitive input.
Table II. AD7304 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format
MSB
B11
LSB
B0
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
AD7304
SAC
SDC
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
If B11 (SAC),
Shutdown All Channels
, is set to logic LOW, all DACs are placed in a power shutdown mode, all output voltages become high resistance. If B10 (SDC),
Shutdown Decoded Channel
,
is set to logic LOW, only the DAC decoded by address bits A1 and A0 is placed in the shutdown mode.
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