VDD = 2.5 V ± 10%, V
參數(shù)資料
型號(hào): AD7357YRUZ-500RL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 18/21頁(yè)
文件大?。?/td> 0K
描述: IC ADC DUAL14BIT 4.2MSPS 16TSSOP
設(shè)計(jì)資源: DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7357 (CN0061)
標(biāo)準(zhǔn)包裝: 500
位數(shù): 14
采樣率(每秒): 4.2M
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 59mW
電壓電源: 單電源
工作溫度: -40°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類(lèi)型: 2 個(gè)差分,雙極
AD7357
Rev. B | Page 5 of 20
TIMING SPECIFICATIONS
VDD = 2.5 V ± 10%, VDRIVE = 2.25 V to 3.6 V, internal reference = 2.048 V, TA = TMAX to TMIN1, unless otherwise noted.
Table 3.
Parameter
Limit at TMIN, TMAX
Unit
Description
fSCLK
500
kHz min
80
MHz max
tCONVERT
t2 + 15.5 × tSCLK
ns min
tSCLK = 1/fSCLK
tQUIET
5
ns min
Minimum time between end of serial read and next falling edge of CS
t2
5
ns min
CS to SCLK setup time
6
ns max
Delay from CS until SDATAA and SDATAB are three-state disabled
Data access time after SCLK falling edge
12.5
ns max
1.8 V ≤ VDRIVE < 2.25 V
11
ns max
2.25 V ≤ VDRIVE < 2.75 V
9.5
ns max
2.75 V ≤ VDRIVE < 3.3 V
9
ns max
3.3 V ≤ VDRIVE ≤ 3.6 V
t5
5
ns min
SCLK low pulse width
t6
5
ns min
SCLK high pulse width
SCLK to data valid hold time
3.5
ns min
1.8 V ≤ VDRIVE < 2.75 V
3
ns min
2.75 V ≤ VDRIVE ≤ 3.6 V
t8
9.5
ns max
CS rising edge to SDATA , SDATAB, high impedance
A
t9
5
ns min
CS rising edge to falling edge pulse width
4.5
ns min
SCLK falling edge to SDATAA, SDATAB, high impedance
9.5
ns max
SCLK falling edge to SDATAA, SDATAB, high impedance
Latency
1 conversion latency
1 Temperature ranges are as follows: AD7357Y: 40°C to +125°C, AD7357B: 40°C to +85°C, AD7357WY: 40°C to +125°C.
2 Specified with a load capacitance of 10 pF on SDATAA and SDATAB.
3 The time required for the output to cross 0.4 V or 2.4 V.
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