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參數(shù)資料
| 型號： | AD7495BRZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SRL LP W/REF 8-SOIC |
| 標準包裝： | 1,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 10.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
AD7475/AD7495
Rev. B | Page 13 of 24
THEORY OF OPERATION
The AD7475/AD7495 are fast, micropower, 12-bit, single-
supply analog-to-digital converters (ADCs). The parts can be
operated from a 2.7 V to 5.25 V supply. When operated from
either a 5 V supply or a 3 V supply, the AD7475/AD7495 are
capable of throughput rates of 1 MSPS when provided with a
20 MHz clock.
The AD7475/AD7495 ADCs have an on-chip track-and-hold
with a serial interface housed in either an 8-lead SOIC_N or
MINI_SO package, features that offer the user considerable
space-saving advantages over alternative solutions. The AD7495
also has an on-chip 2.5 V reference. The serial clock input
accesses data from the part but also provides the clock source
for the successive-approximation ADC. The analog input range
is 0 V to REF IN for the AD7475 and 0 V to REF OUT for the
AD7495.
The AD7475/AD7495 also feature power-down options to allow
power saving between conversions. The power-down feature is
implemented across the standard serial interface, as described
in the Operating Modes section.
CONVERTER OPERATION
The AD7475/AD7495 are 12-bit, successive approximation
analog-to-digital converters based around a capacitive DAC.
The AD7475/AD7495 can convert analog input signals in the
schematics of the ADC. The ADC comprises control logic, SAR,
and a capacitive DAC, which are used to add and subtract fixed
amounts of charge from the sampling capacitor to bring the
comparator back into a balanced condition. Figure 10 shows the
ADC during its acquisition phase. SW2 is closed and SW1 is in
Position A. The comparator is held in a balanced condition and
the sampling capacitor acquires the signal on VIN.
COMPARATOR
VIN
CONTROL LOGIC
CAPACITIVE
DAC
AGND
4k
Ω
SW2
SW1
A
B
01684-B-010
Figure 10. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 11), SW2 opens
and SW1 moves to Position B causing the comparator to
become unbalanced. The control logic and the capacitive DAC
are used to add and subtract fixed amounts of charge from the
sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code.
COMPARATOR
VIN
CONTROL LOGIC
CAPACITIVE
DAC
AGND
4k
Ω
SW2
SW1
A
B
01684-B
-011
Figure 11. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding of the AD7475/AD7495 is straight binary.
The designed code transitions occur midway between
successive LSB integer values (that is, LSB, 3/2 LSBs, etc.). The
LSB size is = VREF/4096. The ideal transfer characteristic for the
AD7475/AD7495 is shown in Figure 12.
111...111
111...110
111...000
011...111
000...010
000...001
000...000
ADC
CODE
0V 0.5LSB
VREF –1.5LSB
ANALOG INPUT
1LSB = VREF/4096
01684-B
-012
Figure 12. AD7475/AD7495 Transfer Characteristic
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