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| 型號(hào)： | AD7641ASTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 18-Bit, 2 MSPS SAR ADC |
| 中文描述： | 1-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | MS-026-BBC, LQFP-48 |
| 文件頁數(shù)： | 16/24頁 |
| 文件大?。?/td> | 324K |
| 代理商： | AD7641ASTRL |
AD7641
Preliminary Technical Data
POWER SUPPLY
The AD7641 uses three sets of power supply pins: an analog 2.5
V supply AVDD, a digital 2.5 V core supply DVDD, and a digital
input/output interface supply OVDD. The OVDD supply allows
direct interface with any logic working between 2.3 V and 5.25
V. To reduce the number of supplies needed, the digital core
(DVDD) can be supplied through a simple RC filter from the
analog supply as shown in Figure 7. The AD7641 is independent
of power supply sequencing and thus free from supply voltage
induced latchup. Additionally, it is very insensitive to power
supply variations over a wide frequency range as shown in
Figure 12.
Rev. Pr E | Page 16 of 24
Figure 12. PSRR vs. Frequency
CONVERSION CONTROL
Figure 13 shows the detailed timing diagrams of the conversion
process. The AD7641 is controlled by the signal CNVST which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conversion
is complete. The CNVST signal operates independently of CS
and RD signals.
CNVST
BUSY
MODE
t2
t1
t3
t4
t5
t6
t7
t8
ACQUIRE
CONVERT
ACQUIRE
CONVERT
Figure 13. Basic Conversion Timing
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges and levels, with minimum
overshoot and undershoot or ringing.
For applications where the SNR is critical, the CNVST signal
should have a very low jitter. Some solutions to achieve that are
to use a dedicated oscillator for CNVST generation or, at least,
to clock it with a high frequency low jitter clock as shown in
Figure 7.
t9
t8
RESET
DATA
BUS
BUSY
CNVST
Figure 14. RESET Timing
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