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參數(shù)資料
| 型號： | AD7641ASTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 18-Bit, 2 MSPS SAR ADC |
| 中文描述： | 1-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | MS-026-BBC, LQFP-48 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 324K |
| 代理商： | AD7641ASTRL |
Preliminary Technical Data
AD7641
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Rev. Pr E | Page 7 of 24
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
D
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
TOP VIEW
(Not to Scale)
AGND
CNVST
PD
RESET
CS
RD
DGND
BUSY
D17
D16
D15
D14
AGND
AVDD
MODE0
MODE1
D0/OB/2C
WARP
NC = NO CONNECT
D1/A0
D2/A1
D3
D4/DIVSCLK[0]
D5/DIVSCLK[1]
AD7641
D
D
D
O
O
D
D
D
D
D
D
P
P
R
T
A
I
A
A
N
I
R
R
NC
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
1, 36, 41,
42
2, 44
AVDD
7, 40
NC
3
MODE0
4
MODE1
Type
1
P
Description
Analog power ground pin.
AGND
P
DI
DI
Input analog power pins. Nominally 2.5 V
No Connect
Data Output Interface mode Selection.
Data Output Interface mode Selection:
Interface MODE #
0
1
2
3
When MODE=0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus and the
data coding is straight binary. In all other modes, this pin allows choice of Straight Binary/Binary
Two’s Complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is
inverted resulting in a two’s complement output from its internal shift register.
Conversion mode selection. When HIGH, this input selects the fastest mode, the maximum
throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full
specified accuracy. When LOW, full accuracy is maintained independent of the minimum conversion
rate.
When MODE=0 (18-bit interface mode), this pin is Bit 1 of the parallel port data output bus. In all other
modes, this input pin controls the form in which data is output as shown in Table 6.
When MODE=0 or MODE=1 (18-bit or 16-bit interface mode), this pin is Bit 2 of the parallel port data
output bus. In all other modes, this input pin controls the form in which data is output as shown in
Table 6.
In all modes except MODE=3, this output is used as Bit 3 of the Parallel Port Data Output Bus. This pin
is always an output regardless of the interface mode.
In all modes except MODE=3, these pins are Bit 4 and Bit 5 of the Parallel Port Data Output Bus.
In MODE=3 (serial mode), when EXT/INT is LOW, and RDC/SDIN is LOW, which serial master read after
convert, these inputs, part of the serial port, are used to slow down if desired the internal serial clock
clocks the data output. In other serial modes, these pins are not used.
MODE0
0
0
1
1
MODE1
0
1
0
1
Description
18-bit Interface
16-bit Interface
Byte Interface
Serial Interface
5
D0/OB/2C
DI/O
6
WARP
DI
8
D1/A0
DI/O
9
D2/A1
DI/O
10
D3
DO
11, 12
D[4:5] or
DIVSCLK[0:
1]
DI/O
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