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參數(shù)資料
| 型號： | AD7641ASTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 18-Bit, 2 MSPS SAR ADC |
| 中文描述： | 1-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | MS-026-BBC, LQFP-48 |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 324K |
| 代理商： | AD7641ASTRL |
AD7641
Preliminary Technical Data
Rev. Pr E | Page 18 of 24
t
3
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
t
28
t
29
t
14
t
18
t
19
t
20
t
21
t
24
t
26
t
27
t
23
t
22
t
16
t
15
1
2
3
16
17
18
D17
D16
D2
D1
D0
X
EXT/INT = 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
t
25
t
30
Figure 19. Master Serial Data Timing for Reading (Read After Convert)
SERIAL INTERFACE
The AD7641 is configured to use the serial interface when
MODE0 and MODE1 are held high. The AD7641 outputs 18
bits of data, MSB first, on the SDOUT pin. This data is
synchronized with the 18 clock pulses provided on SCLK pin.
The output data is valid on both the rising and falling edge of
the data clock. That allows a fast serial interface speed by using
the same clock edge to output the data from the ADC and to
sample the previous bit by the digital host.
MASTER SERIAL INTERFACE
Internal Clock
The AD7641 is configured to generate and provide the serial
data clock SCLK when the EXT/INT pin is held low. The
AD7641 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted if desired. Depending on
RDC/SDIN input, the data can be read after each conversion or
during the following conversion. Figure 19 and Figure 20 show
the detailed timing diagrams of these two modes.
Usually, because the AD7641 is used with a fast throughput, the
mode master read during conversion is the most recommended
serial mode when it can be used.
In read-during-conversion mode, the serial clock and data
toggle at appropriate instants which minimize potential
feedthrough between digital activity and the critical conversion
decisions.
In read-after-conversion mode, it should be noted that, unlike
in other modes, the signal BUSY returns low after the 18 data
bits are pulsed out and not at the end of the conversion phase
which results in a longer BUSY width.
To accommodate slow digital hosts, the serial clock can be
slowed down by using DIVSCLK.
SLAVE SERIAL INTERFACE
External Clock
The AD7641 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/INT pin is
held high. In this mode, several methods can be used to read the
data. The external serial clock is gated by CS When CS and RD
are both low, the data can be read after each conversion or
during the following conversion. The external clock can be
either a continuous or discontinuous clock. A discontinuous
clock can be either normally high or normally low when
inactive. Figure 21 and Figure 22 show the detailed timing
diagrams of these methods.
While the AD7641 is performing a bit decision, it is important
that voltage transients not occur on digital input/output pins or
degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7641 provides error correction circuitry
that can correct for an improper bit decision made during the
first half of the conversion phase. For this reason, it is
recommended that when an external clock is being provided, it
be a discontinuous clock that is toggling only when BUSY is low
or, more importantly, that it does not transition during the latter
half of BUSY high.
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