CREF
參數(shù)資料
型號: AD7641BCPZRL
廠商: Analog Devices Inc
文件頁數(shù): 23/28頁
文件大?。?/td> 0K
描述: IC ADC 18BIT 2MSPS SAR 48-LFCSP
產(chǎn)品培訓模塊: ADC Applications
ADC Architectures
ADC DC/AC Performance
標準包裝: 2,500
位數(shù): 18
采樣率(每秒): 2M
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 92mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應商設備封裝: 48-LFCSP-VQ(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個差分,雙極
配用: EVAL-AD7641CBZ-ND - BOARD EVALUATION FOR AD7641
AD7641
Rev. 0 | Page 4 of 28
Parameter
Conditions
Min
Typ
Max
Unit
Turn-On Settling Time
CREF = 10 μF
5
ms
REFBUFIN Output Voltage
REFBUFIN @ 25°C
1.19
V
REFBUFIN Output Resistance
6.33
EXTERNAL REFERENCE
PDREF = PDBUF = high
Voltage Range
REF
1.8
2.048
AVDD + 0.1
V
Current Drain
2 MSPS throughput
180
μA
REFERENCE BUFFER
PDREF = high, PDBUF = low
REFBUFIN Input Voltage Range
REF = 2.048 V typ
1.05
1.2
1.30
V
REFBUFIN Input Current
REFBUFIN = 1.2 V
1
nA
TEMPERATURE PIN
Voltage Output
@ 25°C
278
mV
Temperature Sensitivity
1
mV/°C
Output Resistance
4.7
DIGITAL INPUTS
Logic Levels
VIL
0.3
+0.6
V
VIH
1.7
5.25
V
IIL
1
+1
μA
IIH
1
+1
μA
DIGITAL OUTPUTS
Data Format7
Pipeline Delay8
VOL
ISINK = 500 μA
0.4
V
VOH
ISOURCE = 500 μA
OVDD 0.3
V
POWER SUPPLIES
Specified Performance
AVDD
2.37
2.5
2.63
V
DVDD
2.37
2.5
2.63
V
OVDD
2.309
3.6
V
Operating Current10
2 MSPS throughput
AVDD11
With internal reference
23
mA
DVDD
2.5
mA
0.5
mA
Power Dissipation11
With Internal Reference10
2 MSPS throughput
75
92
mW
Without Internal Reference10
2 MSPS throughput
68
85
mW
In Power-Down Mode12
PD = high
2
μW
TEMPERATURE RANGE13
Specified Performance
TMIN to TMAX
40
+85
°C
1 When using an external reference. With the internal reference, the input range is 0.1 V to VREF.
3 Linearity is tested using endnotes, not best fit.
4 LSB means least significant bit. With the ±2.048 V input range, 1 LSB is 15.63 μV.
5 See Voltage Reference Input section. These specifications do not include the error contribution from the external reference.
6 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
7 Parallel or serial 18-bit.
8 Conversion results are available immediately after completed conversion.
10 In warp mode. Tested in parallel reading mode.
11 With internal reference, PDREF and PDBUF are low; without internal reference, PDREF and PDBUF are high.
12 With all digital inputs forced to OVDD.
13Consult sales for extended temperature range.
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