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參數(shù)資料
| 型號： | AD7643BSTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 18BIT DIFFER W/REF 48LQFP |
| 標準包裝： | 2,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 1.25M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 80mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 配用： | EVAL-AD7643CBZ-ND - BOARD EVALUATION FOR AD7643 |
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AD7643
Rev. 0 | Page 20 of 28
POWER SUPPLY
The AD7643 uses three sets of power supply pins: an analog
2.5 V supply AVDD, a digital 2.5 V core supply DVDD, and a
digital input/output interface supply OVDD. The OVDD supply
allows direct interface with any logic working between 2.3 V
and 5.25 V. To reduce the number of supplies needed, the digital
core (DVDD) can be supplied through a simple RC filter from
the analog supply, as shown in Figure 23.
Power Sequencing
The AD7643 is independent of power supply sequencing and
thus free from supply induced voltage latch-up. In addition, it is
insensitive to power supply variations over a wide frequency
range, as shown in Figure 29.
65.0
45.0
1
10000
FREQUENCY (kHz)
PS
R
(d
B
)
10
100
1000
62.5
60.0
57.5
55.0
52.5
50.0
47.5
INT REF
EXT REF
06
02
4-
02
9
Figure 29. PSRR vs. Frequency
Power-Up
At power-up, or when returning to operational mode from the
power-down mode (PD = high), the AD7643 engages an
initialization process. During this time, the first 128 conversions
should be ignored or the RESET input could be pulsed to
engage a faster initialization process. Refer to the Digital
Interface section for RESET and timing details.
A simple power-on reset circuit, as shown in Figure 23, can be
used to minimize the digital interface. As OVDD powers up, the
capacitor is shorted and brings RESET high; it is then charged
returning RESET to low. However, this circuit only works when
powering up the AD7643 because the power-down mode
(PD = high) does not power down any of the supplies and as a
result, RESET is low.
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, drive the digital inputs close to
the power rails (that is, OVDD and OGND).
CONVERSION CONTROL
The AD7643 is controlled by the CNVST input. A falling edge
on CNVST is all that is necessary to initiate a conversion.
Detailed timing diagrams of the conversion process are shown
in Figure 30. Once initiated, it cannot be restarted or aborted,
even by the power-down input, PD, until the conversion is
complete. The CNVST signal operates independently of CS and
RD signals.
BUSY
MODE
CONVERT
ACQUIRE
CONVERT
CNVST
t1
t2
t4
t3
t5
t6
t7
t8
06
02
4-
0
30
Figure 30. Basic Conversion Timing
For optimal performance, the rising edge of CNVST should not
occur after the maximum CNVST low time, t1, or until the end
of conversion.
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges and levels with minimum
overshoot and undershoot or ringing.
The CNVST trace should be shielded with ground and a low
value serial resistor (for example, 50 Ω) termination should be
added close to the output of the component that drives this line.
In addition, a 50 pF capacitor is recommended to further reduce
the effects of overshoot and undershoot as shown in Figure 23.
For applications where SNR is critical, the CNVST signal should
have very low jitter. This can be achieved by using a dedicated
oscillator for CNVST generation, or by clocking CNVST with a
high frequency, low jitter clock, as shown in Figure 23.
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