- 您現(xiàn)在的位置：買賣IC網 > PDF目錄10138 > AD7643BSTZRL (Analog Devices Inc)IC ADC 18BIT DIFFER W/REF 48LQFP PDF資料下載
參數(shù)資料
| 型號： | AD7643BSTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 18BIT DIFFER W/REF 48LQFP |
| 標準包裝： | 2,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 1.25M |
| 數(shù)據接口： | 串行，并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 80mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 配用： | EVAL-AD7643CBZ-ND - BOARD EVALUATION FOR AD7643 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
AD7643
Rev. 0 | Page 22 of 28
16-Bit and 8-Bit Interface (Master or Slave)
In the 16-bit (MODE[1:0] = 1) and 8-bit (MODE[1:0] = 2)
interfaces, the A0/A1 pins allow a glueless interface to a 16- or
8-bit bus, as shown in Figure 35. By connecting A0/A1 to an
address line(s), the data can be read in two words for a 16-bit
interface, or three bytes for an 8-bit interface. This interface can
be used in both master and slave parallel reading modes. Refer
to Table 7 for the full details of the interface.
CS, RD
A1
D[17:2]
HI-Z
HIGH
WORD
LOW
WORD
HI-Z
t12
t13
HIGH
BYTE
A0
MID
BYTE
LOW
BYTE
D[17:10]
t12
HI-Z
t12
06
02
4-
0
35
Figure 35. 8-Bit and 16-Bit Parallel Interface
SERIAL INTERFACE
The AD7643 is configured to use the serial interface when
MODE[1:0] = 3. The AD7643 outputs 18 bits of data, MSB first,
on the SDOUT pin. This data is synchronized with the 18 clock
pulses provided on the SCLK pin. The output data is valid on
both the rising and falling edge of the data clock.
MASTER SERIAL INTERFACE
Internal Clock
The AD7643 is configured to generate and provide the serial
data clock SCLK when the EXT/INT pin is held low. The
AD7643 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted. Depending on the read during
convert input, RDC/SDIN, the data can be read after each
conversion or during the following conversion. Figure 36 and
Figure 37 show detailed timing diagrams of these two modes.
Usually, because the AD7643 is used with a fast throughput, the
master read during conversion mode is the most recommended
serial mode. In this mode, the serial clock and data toggle at
appropriate instants, minimizing potential feedthrough between
digital activity and critical conversion decisions. In this mode,
the SCLK period changes because the LSBs require more time
to settle and the SCLK is derived from the SAR conversion cycle.
In read after conversion mode, it should be noted that unlike
other modes, the BUSY signal returns low after the 18 data bits
are pulsed out and not at the end of the conversion phase,
resulting in a longer BUSY width. As a result, the maximum
throughput cannot be achieved in this mode.
In addition, in read after convert mode, the SCLK frequency
can be slowed down to accommodate different hosts using the
DIVSCLK[1:0] inputs. Refer to Table 4 for the SCLK timing
details when using these inputs.
相關PDF資料 |
PDF描述 |
|---|---|
| MS3102R22-20S | CONN RCPT 9POS BOX MNT W/SCKT |
| MS27497E12A35SC | CONN RCPT 22POS WALL MNT W/SCKT |
| PX0931/10/P | CONN JAM NUT 10POS W/PINS |
| LTC2861IGN#TRPBF | IC TXRX RS485 20MBPS 16-SSOP |
| AD7679ACPZRL | IC ADC 18BIT SAR W/BUFF 48LFCSP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD7645AQ | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit Buffered Miltiplying CMOS D/A Converter |
| AD7645BQ | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit Buffered Miltiplying CMOS D/A Converter |
| AD7645CQ | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit Buffered Miltiplying CMOS D/A Converter |
| AD7645GCQ | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit Buffered Miltiplying CMOS D/A Converter |
| AD7645GLN | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit Buffered Miltiplying CMOS D/A Converter |
發(fā)布緊急采購，3分鐘左右您將得到回復。