參數(shù)資料
型號(hào)： AD7643BSTZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 17/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 18BIT DIFFER W/REF 48LQFP
標(biāo)準(zhǔn)包裝： 2,000
系列： PulSAR®
位數(shù)： 18
采樣率（每秒）： 1.25M
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 80mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 1 個(gè)差分，雙極
配用： EVAL-AD7643CBZ-ND - BOARD EVALUATION FOR AD7643
AD7643
Rev. 0 | Page 24 of 28
SLAVE SERIAL INTERFACE
External Clock
The AD7643 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/INT pin is
held high. In this mode, several methods can be used to read
the data. The external serial clock is gated by CS. When CS and
RD are both low, the data can be read after each conversion or
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally high or normally low when
inactive. Figure 39 and Figure 40 show the detailed timing
diagrams of these methods.
While the AD7643 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins
or degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7643 provides error correction circuitry
that can correct for an improper bit decision made during
the first half of the conversion phase. For this reason, it is
recommended that when an external clock is being provided,
a discontinuous clock is toggled only when BUSY is low or,
more importantly, that it does not transition during the latter
half of BUSY high.
External Discontinuous Clock Data Read After Conversion
Figure 39 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
low, the conversion result can be read while both CS and RD are
low. Data is shifted out MSB first with 18 clock pulses and is
valid on the rising and falling edges of the clock.
Among the advantages of this method is the fact that conversion
performance is not degraded because there are no voltage
transients on the digital interface during the conversion process.
Another advantage is the ability to read the data at any speed up
to 80 MHz, which accommodates both the slow digital host
interface and the fast serial reading.
It is also possible to begin to read data after conversion and
continue to read the last bits after a new conversion is initiated.
In this reading mode, it is recommended to pause digital
activity just prior to initiating a conversion (SCLK should be
held high or low). Once the conversion has begun, the reading
can continue. Also, in this mode, the use of a slower clock speed
can be used to read the data because the total reading time is the
acquisition time, t8 + half of the conversion time, t7 (t8 + × t7, see
section).
Finally, in this mode only, the AD7643 provides a daisy-chain
feature using the RDC/SDIN pin for cascading multiple converters
together. This feature is useful for reducing component count
and wiring connections when desired, as, for instance, in
isolated multiconverter applications.
An example of the concatenation of two devices is shown in
Figure 38. Simultaneous sampling is possible by using a
common CNVST signal. It should be noted that the RDC/SDIN
input is latched on the edge of SCLK opposite to the one used to
shift out the data on SDOUT. Therefore, the MSB of the
upstream converter just follows the LSB of the downstream
converter on the next SCLK cycle.
SCLK
SDOUT
RDC/SDIN
AD7643
#1
(DOWNSTREAM)
AD7643
#2
(UPSTREAM)
BUSY
OUT
BUSY
DATA
OUT
SCLK
RDC/SDIN
SDOUT
SCLK IN
CNVST IN
CNVST
CS
CNVST
CS
CS IN
06
02
4-
03
8
Figure 38. Two AD7643 Devices in a Daisy-Chain Configuration
External Clock Data Read During Previous Conversion
Figure 40 shows the detailed timing diagrams of this method.
During a conversion, while CS and RD are both low, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 18 clock pulses and is valid on both the rising
and falling edge of the clock. The 18 bits have to be read before
the current conversion is complete; otherwise, RDERROR is
pulsed high and can be used to interrupt the host interface to
prevent incomplete data reading. There is no daisy-chain
feature in this mode, and the RDC/SDIN input should always
be tied either high or low.
To reduce performance degradation due to digital activity, a fast
discontinuous clock of at least 67 MHz is recommended to
ensure that all the bits are read during the first half of the SAR
conversion phase, t7, because the ADC can correct for errors
introduced by digital activity during this time.
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