參數(shù)資料
型號(hào)： AD7656YSTZ-1-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 17/32頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT 6CH 250KSPS 64LQFP
標(biāo)準(zhǔn)包裝： 1,500
位數(shù)： 16
采樣率（每秒）： 250k
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 6
功率耗散（最大）： 143mW
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 6 個(gè)單端，雙極
配用： EVAL-AD7656-1EDZ-ND - BOARD EVAL CONTROL AD7656-1
EVAL-AD7656-1CBZ-ND - BOARD EVAL FOR AD7656-1
EVAL-AD7656CBZ-ND - BOARD EVAL FOR AD7656
AD7656-1/AD7657-1/AD7658-1
Data Sheet
Rev. D | Page 24 of 32
SOFTWARE SELECTION OF ADCS
The H/S SEL pin determines the source of the combination of ADCs
that are to be simultaneously sampled. When the H/S SEL pin
is logic low, the combination of channels to be simultaneously
sampled is determined by the CONVST A, CONVST B, and
CONVST C pins. When the H/S SEL pin is logic high, the
combination of channels selected for simultaneous sampling
is determined by the contents of the DB15 to DB13 control
registers. In this mode, a write to the control register is necessary.
The control register is an 8-bit write-only register. Data is written
to this register using the CS and WR pins and the DB[15:8] data
pins (see Figure 31). The control register is detailed in Table 10
and Table 11. To select an ADC pair to be simultaneously sampled,
set the corresponding data line high during the write operation.
DATA
DB15 TO DB8
CS
t13
t15
t14
t11
t12
WR
07017-
029
Figure 31. Parallel Interface—Write Cycle for Word Mode (W/B = 0)
The AD7656-1/AD7657-1/AD7658-1 control register allows
individual ranges to be programmed on each ADC pair. DB12
to DB10 in the control register are used to program the range
on each ADC pair.
After a reset occurs on the AD7656-1/AD7657-1/AD7658-1,
the control register contains all 0s.
The CONVST A signal is used to initiate a simultaneous
conversion on the combination of channels selected via the
control register. The CONVST B and CONVST C signals can be
tied low when operating in software mode (H/S SEL = 1). The
number of read pulses required depends on the number of
ADCs selected in the control register and on whether the
devices are operating in word or byte mode. The conversion
results are output in ascending order.
During the write operation, Data Bus Bit DB15 to Data Bus Bit DB8
are bidirectional and become inputs to the control register when
RD is logic high and CS and WR are logic low. The logic state
on DB15 through DB8 is latched into the control register when
WR goes logic high.
Table 10. Control Register Bit Map1
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
VC
VB
VA
RNGC
RNGB
RNGA
REFEN
REFBUF
1
Default all 0s.
Table 11. Control Register Bit Function Descriptions
Bit
Mnemonic
Description
DB15
VC
This bit is used to select the V5 and V6
analog inputs for the next conversion.
When this bit is set to 1, V5 and V6 are
simultaneously converted on the next
CONVST A rising edge.
DB14
VB
This bit is used to select the V3 and V4
analog inputs for the next conversion.
When this bit is set to 1, V3 and V4 are
simultaneously converted on the next
CONVST A rising edge.
DB13
VA
This bit is used to select the V1 and V2
analog inputs for the next conversion.
When this bit is set to 1, V1 and V2 are
simultaneously converted on the next
CONVST A rising edge.
DB12
RNGC
This bit is used to select the analog input
range for the V5 and V6 analog inputs.
When this bit is set to 1, the ±2 × VREF range
is selected for the next conversion. When
this bit is set to 0, the ±4 × VREF range is
selected for the next conversion.
DB11
RNGB
This bit is used to select the analog input
range for the V3 and V4 analog inputs.
When this bit is set to 1, the ±2 × VREF range
is selected for the next conversion. When
this bit is set to 0, the ±4 × VREF range is
selected for the next conversion.
DB10
RNGA
This bit is used to select the analog input
range for the V1 and V2 analog inputs.
When this bit is set to 1, the ±2 × VREF range
is selected for the next conversion. When
this bit is set to 0, the ±4 × VREF range is
selected for the next conversion.
DB9
REFEN
This bit is used to select the internal
reference or an external reference. When
this bit is set to 0, the external reference
mode is selected. When this bit is set to 1,
the internal reference is selected.
DB8
REFBUF
This bit is used to select between using the
internal reference buffers and choosing
to bypass these reference buffers. When
this bit is set to 0, the internal reference
buffers are enabled and decoupling is
required on the REFCAPx pins. When this
bit is set to 1, the internal reference buffers
are disabled and a buffered reference
should be applied to the REFCAPx pins.
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