參數(shù)資料
型號(hào)： AD7656YSTZ-1-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 3/32頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT 6CH 250KSPS 64LQFP
標(biāo)準(zhǔn)包裝： 1,500
位數(shù)： 16
采樣率（每秒）： 250k
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 6
功率耗散（最大）： 143mW
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 6 個(gè)單端，雙極
配用： EVAL-AD7656-1EDZ-ND - BOARD EVAL CONTROL AD7656-1
EVAL-AD7656-1CBZ-ND - BOARD EVAL FOR AD7656-1
EVAL-AD7656CBZ-ND - BOARD EVAL FOR AD7656
Data Sheet
AD7656-1/AD7657-1/AD7658-1
Rev. D | Page 11 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64
DB15
63
W
R/
RE
F
E
N/
DI
S
62
H
/S
SE
L
61
SER
/P
AR
S
E
L
60
A
V
CC
59
AG
ND
58
RE
F
CAP
C
57
AG
ND
56
RE
F
CAP
B
55
AG
ND
54
RE
F
CA
P
A
53
AG
ND
52
AG
ND
51
R
E
FIN
/R
E
FOU
T
50
A
V
CC
49
AG
ND
47
AVCC
46
AVCC
45
V5
42
V4
43
AGND
44
AGND
48
V6
41
AVCC
40
AVCC
39
V3
37
AGND
36
V2
35
AVCC
34
AVCC
33
V1
38
AGND
2
DB13
3
DB12
4
DB11
7
DB8/DOUT A
6
DB9/DOUT B
5
DB10/DOUT C
1
DB14/REFBUFEN/DIS
8
DGND
9
VDRIVE
10
DB7/HBEN/DCEN
12
DB5/DCIN A
13
DB4/DCIN B
14
DB3/DCIN C
15
DB2/SEL C
16
DB1/SEL B
11
DB6/SCLK
17
DB0/
S
E
L
A
18
BUS
Y
19
CS
20
RD
21
CO
NV
S
T
C
22
CO
NV
S
T
B
23
CO
NV
S
T
A
24
ST
B
Y
25
DG
ND
26
DV
CC
27
RANG
E
28
R
ESET
29
W/B
30
V
SS
31
V
DD
32
AG
ND
PIN 1
AD7656-1/AD7657-1/AD7658-1
TOP VIEW
(Not to Scale)
07017-
003
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Description
54, 56, 58
REFCAPA, REFCAPB,
REFCAPC
Reference Capacitor A, Reference Capacitor B, and Reference Capacitor C. Decoupling capacitors are
connected to these pins to decouple the reference buffer for each ADC pair. Decouple each REFCAP pin
to AGND using a 1 F capacitor.
33, 36, 39,
42, 45, 48
V1 to V6
Analog Input 1 to Analog Input 6. These pins are single-ended analog inputs. In hardware mode,
the analog input range of these channels is determined by the RANGE pin. In software mode, it is
determined by the RNGC to RNGA bits of the control register (see Table 11).
32, 37, 38, 43,
44, 49, 52, 53,
55, 57, 59
AGND
Analog Ground. This pin is the ground reference point for all analog circuitry on the AD7656-1/
AD7657-1/AD7658-1. Refer all analog input signals and external reference signals to this pin.
Connect all AGND pins to the AGND plane of the system. The AGND and DGND voltages should
ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.
26
DVCC
Digital Power, 4.75 V to 5.25 V. The DVCC and AVCC voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis. Decouple this supply to DGND by
placing a 1 F decoupling capacitor on the DVCC pin.
9
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines the operating voltage of the
interface. This pin is nominally at the same supply as the supply of the host interface.
8, 25
DGND
Digital Ground. This is the ground reference point for all digital circuitry on the AD7656-1/AD7657-1/
AD7658-1. Connect both DGND pins to the DGND plane of a system. The DGND and AGND voltages
should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient
basis.
34, 35, 40,
41, 46, 47,
50, 60
AVCC
Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the ADC cores. The AVCC and
DVCC voltages should ideally be at the same potential and must not be more than 0.3 V apart, even
on a transient basis.
21, 22, 23
CONVST C,
CONVST B, CONVST A
Conversion Start Input A, Conversion Start Input B, and Conversion Start Input C. These logic inputs
are used to initiate conversions on the ADC pairs. CONVST A is used to initiate simultaneous conversions
on V1 and V2. CONVST B is used to initiate simultaneous conversions on V3 and V4. CONVST C is
used to initiate simultaneous conversions on V5 and V6. When one of these pins switches from low
to high, the track-and-hold switch on the selected ADC pair switches from track to hold, and the
conversion is initiated. These inputs can also be used to place the ADC pairs into partial power-
down mode.
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