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參數(shù)資料
| 型號(hào)： | AD7671ASTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 11/24頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT CMOS 1MSPS 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 125mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個(gè)單端，單極；4 個(gè)單端，雙極 |
| 配用： | EVAL-AD7671CBZ-ND - BOARD EVALUATION FOR AD7671 |
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AD7671
–19–
CS, RD
SCLK
SDOUT
D15
D14
D1
D0
D13
X15
X14
X13
X1
X0
Y15
Y14
BUSY
SDIN
INVSCLK = 0
t35
t36 t37
t31
t32
t16
t33
t34
X15
X14
X
12
3
14
15
1617
18
EXT/
INT = 1
RD = 0
Figure 19. Slave Serial Data Timing for Reading (Read after Convert)
the AD7671 provides error correction circuitry that can correct
for an improper bit decision made during the first half of the
conversion phase. For this reason, it is recommended that when
an external clock is being provided, it is a discontinuous clock
that is toggling only when BUSY is LOW or, more importantly,
that does not transition during the latter half of BUSY HIGH.
External Discontinuous Clock Data Read after Conversion
Though the maximum throughput cannot be achieved using this
mode, it is the most recommended of the serial slave modes.
Figure 19 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning LOW,
the result of this conversion can be read while both
CS and RD
are LOW. The data is shifted out, MSB first, with 16 clock
pulses and is valid on both the rising and falling edge of the clock.
Among the advantages of this method, the conversion perfor-
mance is not degraded because there are no voltage transients
on the digital interface during the conversion process.
Another advantage is to be able to read the data at any speed up to
40 MHz, which accommodates both slow digital host interface
and the fastest serial reading.
Finally, in this mode only, the AD7671 provides a “daisy-chain”
feature using the RDC/SDIN input pin for cascading multiple
converters together. This feature is useful for reducing component
count and wiring connections when desired as, for instance, in
isolated multiconverter applications.
An example of the concatenation of two devices is shown in Fig-
ure 20. Simultaneous sampling is possible by using a common
CNVST signal. It should be noted that the RDC/SDIN input is
latched on the opposite edge of SCLK of the one used to shift out
the data on SDOUT. Therefore, the MSB of the “upstream”
converter just follows the LSB of the “downstream” converter
on the next SCLK cycle.
CNVST
CS
SCLK
SDOUT
RDC/SDIN
BUSY
DATA
OUT
AD7671
#1
(DOWNSTREAM)
BUSY
OUT
CNVST
CS
SCLK
AD7671
#2
(UPSTREAM)
RDC/SDIN
SDOUT
SCLK IN
CS IN
CNVST IN
Figure 20. Two AD7671s in a Daisy-Chain Configuration
External Clock Data Read during Conversion
Figure 21 shows the detailed timing diagrams of this method.
During a conversion, while both
CS and RD are LOW, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 16 clock pulses and is valid on both the rising and
the falling edge of the clock. The 16 bits have to be read before the
current conversion is complete. If that is not done, RDERROR
is pulsed HIGH and can be used to interrupt the host interface
to prevent incomplete data reading. There is no daisy-chain feature
in this mode, and RDC/SDIN input should always be tied either
HIGH or LOW.
REV. C
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD7672 | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS HIGH-SPEED 12-BIT ADC |
| AD7672BE03 | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS HIGH-SPEED 12-BIT ADC |
| AD7672BQ03 | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS HIGH-SPEED 12-BIT ADC |
| AD7672BQ03/+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 12-Bit |
| AD7672BQ05 | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS HIGH-SPEED 12-BIT ADC |
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