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參數資料
| 型號： | AD7686CCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 13/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT SAR 500KSPS 10LFCSP |
| 標準包裝： | 5,000 |
| 系列： | PulSAR® |
| 位數： | 16 |
| 采樣率（每秒）： | 500k |
| 數據接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 21.5mW |
| 電壓電源： | 模擬和數字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤，CSP |
| 供應商設備封裝： | 10-LFCSP-WD（3x3） |
| 包裝： | 帶卷 (TR) |
| 輸入數目和類型： | 1 個偽差分，單極 |
| 配用： | EVAL-AD7686CBZ-ND - BOARD EVALUATION FOR AD7686 |
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AD7686
Rev. B | Page 20 of 28
CS MODE 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7686 is connected
to an SPI-compatible digital host, which has an interrupt input,
and when it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This requirement is particularly important in applications
where low jitter on CNV is desired. The connection diagram is
shown in Figure 39, and the corresponding timing is provided
in Figure 40.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time and held low until the maximum conversion time to
guarantee the generation of the busy signal indicator. When
conversion is complete, SDO goes from high impedance to low.
With a pull-up on the SDO line, this transition can be used as
an interrupt signal to initiate the data readback controlled by
the digital host. The AD7686 then enters the acquisition phase
and powers down. The data bits are then clocked out, MSB first,
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the optional
17th SCK falling edge or SDI going high, whichever occurs first,
the SDO returns to high impedance.
DATA IN
IRQ
CLK
CONVERT
CS1
VIO
DIGITAL HOST
02
96
9-
04
0
47k
CNV
SCK
SDO
SDI
AD7686
Figure 39. CS Mode 4-Wire with Busy Indicator Connection Diagram
SDO
D15
D14
D1
D0
tDIS
SCK
1
2
3
151617
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI
CNV
tSSDICNV
tHSDICNV
02
96
9-
0
41
Figure 40. CS Mode 4-Wire with Busy Indicator Serial Interface Timing
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7686CCPZRL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 500 kSPS PulSAR ADC in MSOP/QFN |
| AD7686CCPZRL7 | 功能描述:IC ADC 16BIT SAR 500KSPS 10LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:PulSAR® 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7686CCPZRL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 500 kSPS PulSAR ADC in MSOP/QFN |
| AD7686CRM | 制造商:Analog Devices 功能描述:ADC Single SAR 500ksps 16-bit Serial 10-Pin MSOP Tube |
| AD7686CRMRL7 | 制造商:Analog Devices 功能描述:ADC Single SAR 500ksps 16-bit Serial 10-Pin MSOP T/R |
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