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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | AD7693BRMZRL7 |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 22/24闋�(y猫) |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC ADC 16BIT 500KSPS 10-MSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1,000 |
| 绯诲垪锛� | PulSAR® |
| 浣嶆暩(sh霉)锛� | 16 |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 500k |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | DSP锛孧ICROWIRE?锛孮SPI?锛屼覆琛岋紝SPI? |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 1 |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 21.5mW |
| 闆诲闆绘簮锛� | 妯℃摤鍜屾暩(sh霉)瀛� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 10-TFSOP锛�10-MSOP锛�0.118"锛�3.00mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 10-MSOP |
| 鍖呰锛� | 甯跺嵎 (TR) |
| 杓稿叆鏁�(sh霉)鐩拰椤炲瀷锛� | 1 鍊�(g猫)宸垎锛岄洐妤� |
| 閰嶇敤锛� | EVAL-AD7693CBZ-ND - BOARD EVALUATION FOR AD7693 |
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)绗�21闋�(y猫)鐣�(d膩ng)鍓嶇22闋�(y猫)绗�23闋�(y猫)绗�24闋�(y猫)
AD7693
Rev. A | Page 7 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF 1
VDD 2
IN+ 3
IN鈥� 4
GND 5
VIO
10
SDI
9
SCK
8
SDO
7
CNV
6
AD7693
TOP VIEW
(Not to Scale)
06
39
4-
00
5
Figure 5. 10-Lead MSOP Pin Configuration
1
REF
2
VDD
3
IN+
4
IN鈥�
5
GND
NOTES
1. THE EXPOSED PAD IS CONNECTED
TO GND. THIS CONNECTION IS NOT
REQUIRED TO MEET THE ELECTRICAL
PERFORMANCES.
10 VIO
9SDI
8SCK
7SDO
6CNV
TOP VIEW
(Not to Scale)
AD7693
05
793-
006
Figure 6. 10-Lead QFN (LFCSP) Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1
REF
AI
Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This
pin should be decoupled closely to the pin with a 10 渭F capacitor.
2
VDD
P
Power Supply.
3
IN+
AI
Differential Positive Analog Input.
4
IN
AI
Differential Negative Analog Input.
5
GND
P
Power Supply Ground.
6
CNV
DI
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions
and selects the interface mode of the part: chain or CS mode. In chain mode, the data should be
read when CNV is high. In CS mode, the SDO pin is enabled when CNV is low.
7
SDO
DO
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8
SCK
DI
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this
clock.
9
SDI
DI
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC
as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a
data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line.
The digital data level on SDI is output on SDO with a delay of 16 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV
can enable the serial output signals when low and if SDI or CNV is low when the conversion is
complete, the busy indicator feature is enabled.
10
VIO
P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V,
2.5 V, 3 V, or 5 V).
EPAD
Exposed Pad. The exposed pad is connected to GND. This connection is not required to meet
the electrical performances. The exposed pad is only on the 10-Lead QFN (LFCSP).
1AI = analog input, DI = digital input, DO = digital output, and P = power.
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