參數(shù)資料
型號(hào): AD7707BRZ-REEL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 31/52頁(yè)
文件大?。?/td> 0K
描述: IC ADC 16BIT 3CHAN 20SOIC
標(biāo)準(zhǔn)包裝: 400
位數(shù): 16
采樣率(每秒): 500
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 1mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC W
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)單端,單極;1 個(gè)單端,雙極;2 個(gè)偽差分,單極;2 個(gè)偽差分,雙極
AD7707
Rev. B | Page 37 of 52
CONFIGURING THE AD7707
The AD7707 contains six on-chip registers that the user can
accesses via the serial interface. Communication with any of
these registers is initiated by writing to the communications
register first. Figure 22 outlines a flow diagram of the sequence
used to configure all registers after a power-up or reset on the
AD7707. The flowchart also shows two different read options—
the first in which the DRDY pin is polled to determine when an
update of the data register has taken place, the second in which
the DRDY bit of the communications register is interrogated to
determine if a data register update has taken place. Also included
in the flowing diagram is a series of words that should be writ-
ten to the registers for a particular set of operating conditions.
These conditions are gain of 1, no filter sync, bipolar mode,
buffer off, clock of 4.9512 MHz, and an output rate of 50 Hz.
DOUT
SCLK
CS
DRDY
MSB
t5
t7
t8
t9
LSB
t6
t3
t4
t10
08
69
1-
0
20
Figure 20. Read Cycle Timing Diagram
DIN
SCLK
CS
MSB
LSB
t11
t12
t15
t16
t13
t14
08
69
1-
02
1
Figure 21. Write Cycle Timing Diagram
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