參數(shù)資料
型號(hào)： AD7718BRZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/44頁(yè)
文件大?。?/td> 0K
描述： IC ADC 24BIT R-R 8/10CH 28SOIC
標(biāo)準(zhǔn)包裝： 400
位數(shù)： 24
采樣率（每秒）： 1.37k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 3.84mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 5 個(gè)差分，單極；5 個(gè)差分，雙極；10 偽差分，單極；10 偽差分，雙極
配用： EVAL-AD7718EBZ-ND - BOARD EVALUATION FOR AD7718
REV. 0
–26–
AD7708/AD7718
Status Register (A3, A2, A1, A0 = 0, 0, 0, 0; Power-On-Reset = 00Hex)
The ADC Status Register is an 8-bit read-only register. To access the ADC Status Register, the user must write to the Communica-
tions Register selecting the next operation to be a read and load Bits A3-A0 with 0, 0, 0,0. Table XIV outlines the bit designations
for the Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 denotes the
first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
R
S7
6
R
S5
R
S4
R
S3
R
S2
R
S1
R
S0
R
S
Y
D
R)
0
()
0
(
0)
0
(
L
A
C)
0
(
0)
0
(
R
E)
0
(
0)
0
(
0)
0
(
K
C
O
L
Table XIV. Status Register Bit Designations
Bit
Location
Mnemonic Description
SR7
RDY
Ready Bit for the ADC
Set when data is transferred to the ADC data registers or on completion of calibration cycle. The RDY
bit is cleared automatically a period of time before the data register is updated with a new conversion
result or after the ADC data register has been read. This bit is also cleared by a write to the mode bits to
indicate a conversion or calibration. The
RDY pin is the complement of the RDY bit.
SR6
0
Bit is automatically cleared. Reserved for future use
SR5
CAL
Calibration Status Bit
Set to indicate completion of calibration. It is set at the same time that the RDY is set high.
Cleared by a write to the mode bits to start another ADC conversion or calibration.
SR4
0
This bit is automatically cleared. Reserved for future use
SR3
ERR
ADC Error Bit
Set to indicate that the result written to the ADC data register has been clamped to all zeros or all ones.
After a calibration this bit also flags error conditions that caused the calibration registers not to be
written. Error sources include Overrange.
Cleared by a write to the mode bits to initiate a conversion or calibration.
SR2
0
This bit is automatically cleared. Reserved for future use
SR1
0
This bit is automatically cleared. Reserved for future use
SR0
LOCK
PLL Lock Status Bit.
Set if the PLL has locked onto the 32.768 kHz crystal oscillator clock. If the user is worried about
exact sampling frequencies etc., the LOCK bit should be interrogated and the result discarded if the
LOCK bit is zero.
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