參數(shù)資料
型號(hào)： AD7718BRZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 9/44頁
文件大?。?/td> 0K
描述： IC ADC 24BIT R-R 8/10CH 28SOIC
標(biāo)準(zhǔn)包裝： 400
位數(shù)： 24
采樣率（每秒）： 1.37k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 3.84mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 5 個(gè)差分，單極；5 個(gè)差分，雙極；10 偽差分，單極；10 偽差分，雙極
配用： EVAL-AD7718EBZ-ND - BOARD EVALUATION FOR AD7718
REV. 0
AD7708/AD7718
–17–
FREQUENCY – Hz
0
–80
–160
0
100
10
A
TTENUA
TION
–
dB
20
30
40
50
60
70
80
90
–20
–40
–120
–140
–60
–100
SF = 255
OUTPUT DATA RATE = 5.35Hz
INPUT BANDWIDTH = 1.28Hz
50Hz REJECTION = –93dB, 50Hz 1Hz REJECTION = –93dB
60Hz REJECTION = –74dB, 60Hz 1Hz REJECTION = –68dB
Figure 7. Filter Profile with SF = 255
FREQUENCY – Hz
0
–80
–160
0
100
10
A
TTENUA
TION
–
dB
20
30
40
50
60
70
80
90
–20
–40
–120
–140
–60
–100
SF = 69
OUTPUT DATA RATE = 19.8Hz
INPUT BANDWIDTH = 4.74Hz
FIRST NOTCH = 9.9Hz
50Hz REJECTION = –66dB, 50Hz 1Hz REJECTION = –60dB
60Hz REJECTION = –117dB, 60Hz 1Hz REJECTION = –94dB
Figure 8. Filter Profile with Default SF = 69 Giving Filter
Notches at Both 50 Hz and 60 Hz
FREQUENCY – Hz
0
–80
–160
0
100
10
A
TTENUA
TION
–
dB
20
30
40
50
60
70
80
90
–20
–40
–120
–140
–60
–100
SF = 68
OUTPUT DATA RATE = 20.07Hz
INPUT BANDWIDTH = 4.82Hz
50Hz REJECTION = –74dB, 50Hz 1Hz REJECTION = –54.6dB
60Hz REJECTION = –147dB, 60Hz 1Hz REJECTION = –101dB
Figure 9. Filter Profile with SF = 68
ADC NOISE PERFORMANCE CHOP ENABLED
(
CHOP = 0)
Tables II to V show the output rms noise and output peak-to-
peak resolution in bits (rounded to the nearest 0.5 LSB) for a
selection of output update rates. The numbers are typical and
generated at a differential input voltage of 0 V with AVDD =
DVDD = 5 V and using a 2.5 V reference. The output update
rate is selected via the SF7–SF0 bits in the Filter Register. It is
important to note that the peak-to-peak resolution figures repre-
sent the resolution for which there will be no code flicker within
a six-sigma limit. The output noise comes from two sources. The
first is the electrical noise in the semiconductor devices (device
noise) used in the implementation of the modulator. Secondly,
when the analog input is converted into the digital domain,
quantization noise is added. The device noise is at a low level
and is independent of frequency. The quantization noise starts at
an even lower level but rises rapidly with increasing frequency to
become the dominant noise source. The numbers in the tables
are given for the bipolar input ranges. For the unipolar ranges
the rms noise numbers will be the same as the bipolar range, but
the peak-to-peak resolution is now based on half the signal range
which effectively means losing one bit of resolution.
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