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參數(shù)資料
| 型號： | AD7718BRZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT R-R 8/10CH 28SOIC |
| 標(biāo)準(zhǔn)包裝： | 400 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 1.37k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 3.84mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 5 個差分，單極；5 個差分，雙極；10 偽差分，單極；10 偽差分，雙極 |
| 配用： | EVAL-AD7718EBZ-ND - BOARD EVALUATION FOR AD7718 |
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REV. 0
AD7708/AD7718
–29–
AD0C2
RN2
ADC Range Bits
AD0C1
RN1
Written by the user to select the ADC input range as follows
AD0C0
RN0
RN2
RN1
RN0
Selected ADC Input Range (VREF = 2.5 V)
000
±20 mV
001
±40 mV
010
±80 mV
011
±160 mV
100
±320 mV
101
±640 mV
110
±1.28 V
111
±2.56 V
Filter Register (A3, A2, A1, A0 = 0, 0, 1, 1; Power-On Reset = 45Hex)
The Filter Register is an 8-bit register from which data can be read or to which data can be written. This register determines the
amount of averaging performed by the sinc filter. Table XVII outlines the bit designations for the Filter Register. FR7 through FR0
indicate the bit location, FR denoting the bits are in the Filter Register. FR7 denotes the first bit of the data stream. The number in
brackets indicates the power-on/reset default status of that bit. The number in this register is used to set the decimation factor and
thus the output update rate for the ADCs. The filter register cannot be written to by the user the ADC is active. The update rate is
used for the ADCs is calculated as follows:
f
CHOP Enabled CHOP
f
SF
f
CHOP Disabled CHOP
ADC
MOD
ADC
MOD
=×
=
×
×=
()
1
3
0
1
8
1
where
fADC = ADC Output Update Rate,
fMOD = Modulator Clock Frequency = 32.768 kHz,
SF
= Decimal Value Written to SF Register.
Table XVII. Filter Register Bit Designations
7
R
F6
R
F5
R
F4
R
F3
R
F2
R
F1
R
F0
R
F
)
0
(
7
F
S6
F
S)
1
(5
F
S)
0
(4
F
S)
0
(3
F
S)
0
()
1
(
2
F
S)
0
(
1
F
S)
1
(
0
F
S
The allowable range for SF is 13 decimal to 255 decimal with chop enabled, and the allowable SF range when chop is disabled is 03
decimal to 255 decimal. Examples of SF values and corresponding conversion rate (fADC) and time (tADC) are shown in Table XVIII.
It should be noted that optimum performance is obtained when operating with chop enabled. When chopping is enabled (
CHOP = 0),
the filter register is loaded with FF HEX during a calibration cycle. With chop disabled (
CHOP =1), the value in the filter register is
used during calibration.
Table XVIII. Update Rate vs. SF Word
CHOP Enabled
CHOP Disabled
SF (Dec)
SF (Hex)
fADC (Hz)
tADC (ms)
fADC (Hz)
tADC (ms)
03
N/A
1365.33
0.732
13
0D
105.3
9.52
315
3.17
69
45
19.79
50.34
59.36
16.85
255
FF
5.35
186.77
16.06
62.26
Table XVI. ADC Control Register (ADCCON) Bit Designations (continued)
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