During power-on, the VOUT pins o" />
參數(shù)資料
型號: AD7835AP
廠商: Analog Devices Inc
文件頁數(shù): 10/28頁
文件大?。?/td> 0K
描述: IC DAC 14BIT QUAD PARA 44-PLCC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1
設(shè)置時間: 10µs
位數(shù): 14
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 模擬和數(shù)字,雙 ±
功率耗散(最大): 465mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 管件
輸出數(shù)目和類型: 4 電壓,單極;4 電壓,雙極
采樣率(每秒): 100k
AD7834/AD7835
Rev. D | Page 18 of 28
DSG VOLTAGE RANGE
During power-on, the VOUT pins of the AD7834/AD7835 are
connected to the relevant DSG pins via G6 and the thin-film
resistor, R. The DSG potential must obey the maximum ratings
at all times. Thus, the voltage at DSG must always be within the
range VSS – 0.3 V to VDD + 0.3 V. However, to keep the voltages
at the VOUT pins of the AD7834/AD7835 within ±2 V of the
relevant DSG potential during power-on, the voltage applied to
DSG should also be kept within the range AGND – 2 V to
AGND + 2 V.
Once the AD7834/AD7835 have powered on and the on-chip
amplifiers have settled, the situation is as shown in Figure 23.
Any voltage subsequently applied to the DSG pin is buffered by
the same amplifier that buffers the DAC output voltage in
normal operation. Thus, for specified operations, the maximum
voltage applied to the DSG pin increases to the maximum
allowable VREF(+) voltage, and the minimum voltage applied to
DSG is the minimum VREF() voltage. After the AD7834 or
AD7835 has fully powered on, the outputs can track any DSG
voltage within this minimum/maximum range.
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