參數(shù)資料
型號(hào)： AD7835AP
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/28頁(yè)
文件大?。?/td> 0K
描述： IC DAC 14BIT QUAD PARA 44-PLCC
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 10µs
位數(shù)： 14
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 模擬和數(shù)字，雙 ±
功率耗散（最大）： 465mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC（16.59x16.59）
包裝： 管件
輸出數(shù)目和類型： 4 電壓，單極；4 電壓，雙極
采樣率（每秒）： 100k
AD7834/AD7835
Rev. D | Page 22 of 28
INTERFACING THE AD7835—8-BIT INTERFACE
When writing to the DACs, the lower eight bits must be written
first, followed by the upper six bits. The upper six bits should be
output on data lines D0 to D5. Once again, the upper address
lines of the processor are decoded to provide a
Figure 32 shows an 8-bit interface between the AD7835 and
a generic 8-bit microcontroller/DSP processor. Pin D13 to
Pin D8 of the AD7835 are tied to DGND. Pin D7 to Pin D0 of the
processor are connected to Pin D7 to Pin D0 of the AD7835.
CS signal. They
are also decoded in conjunction with lines A3 to A0 to provide
an
BYSHF is driven by the A0 line of the processor. This maps the
DAC upper bits and lower bits into adjacent bytes in the proces-
sor address space. Table 14 shows the truth table for addressing
the DACs in the AD7835. For example, if the base address for the
DACs in the processor address space is decoded by the upper
address bits to location HC000, then the upper and lower bits of
the first DAC are at locations HC000 and HC001, respectively.
ADDRESS
DECODE
D7
D0
A2
A1
A0
R/W
DATABUS
UPPER BITS OF
ADDRESS BUS
A3
AD78351
D7
D0
CS
LDAC
A2
A1
A0
BYSHF
D13
D8
DGND
WR
1ADDITIONAL PINS OMITTED FOR CLARITY
MICROCONTROLLER/
DSP
PROCESSOR1
01
00
6-
03
2
Figure 32. AD7835 8-Bit Interface
LDAC
signal. Alternatively,
can be driven by an exter-
nal timing circuit or, if it is acceptable to allow the DAC output
to go to an intermediate value between 8-bit writes, LDAC can
be tied low.
Table 14. DAC Channel Decoding, 8-Bit Interface
Processor Address Lines
A3
A2
A1
A0
DAC Selected
x
X
0
Upper 6 bits of all DACs
1
X
1
Lower 8 bits of all DACs
0
Upper 6 bits, DAC 1
0
1
Lower 8 bits, DAC 1
0
1
0
Upper 6 bits, DAC 2
0
1
Lower 8 bits, DAC 2
0
1
0
Upper 6 bits, DAC 3
0
1
0
1
Lower 8 bits, DAC 3
0
1
0
Upper 6 bits, DAC 4
0
1
Lower 8-bits, DAC 4
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